Move address calculation to ID.
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parent
e0b6634a93
commit
3216c89dae
7 changed files with 52 additions and 6 deletions
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@ -90,6 +90,7 @@ class CPU extends MultiIOModule {
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IDBarrier.in.r2Address := ID.io.r2Address
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IDBarrier.in.ALUop := ID.io.ALUOp
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IDBarrier.in.returnAddr := ID.io.returnAddr
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IDBarrier.in.branchAddr := ID.io.branchAddr
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IDBarrier.in.jump := ID.io.jump
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IDBarrier.in.branchType := ID.io.branchType
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IDBarrier.in.writeEnable := ID.io.writeEnableOut
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@ -109,6 +110,7 @@ class CPU extends MultiIOModule {
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EXBarrier.branchIn := EX.io.branch
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EXBarrier.in.jump := IDBarrier.out.jump
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EXBarrier.in.returnAddr := IDBarrier.out.returnAddr
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EXBarrier.branchAddrIn := IDBarrier.out.branchAddr
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EXBarrier.in.writeEnable := IDBarrier.out.writeEnable
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EXBarrier.in.writeAddr := IDBarrier.out.writeAddr
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EXBarrier.in.memWrite := IDBarrier.out.memWrite
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@ -126,6 +128,12 @@ class CPU extends MultiIOModule {
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MEMBarrier.in.writeEnable := EXBarrier.out.writeEnable
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MEMBarrier.in.writeAddr := EXBarrier.out.writeAddr
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// Fast branching forwarding
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ID.io.forwardEx := EXBarrier.forwardEx
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ID.io.forwardMem := MEMBarrier.forwardMem
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ID.io.forwardWb := MEMBarrier.forwardWb
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ID.io.forwardId := MEMBarrier.forwardId
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// Write back
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ID.io.writeData := MEMBarrier.out.data
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ID.io.writeEnableIn := MEMBarrier.out.writeEnable
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@ -133,7 +141,7 @@ class CPU extends MultiIOModule {
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// Branching
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IF.io.branch := EXBarrier.branchOut
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IF.io.branchAddress := EXBarrier.branchAddr
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IF.io.branchAddress := EXBarrier.branchAddrOut
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// Stall
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IF.io.stall := IDBarrier.stall
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@ -87,7 +87,7 @@ class Decoder() extends Module {
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// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
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JAL -> List(Y, N, N, Y, Y, branchType.jump, PC, imm, ImmFormat.JTYPE, ALUOps.ADD ),
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JALR -> List(Y, N, N, Y, Y, branchType.jump, rs1, imm, ImmFormat.ITYPE, ALUOps.ADDR ),
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JALR -> List(Y, N, N, Y, Y, branchType.jump, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ),
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)
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@ -31,7 +31,6 @@ class Execute extends MultiIOModule {
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ALUOps.SRA -> (io.op1 >> io.op2(4, 0)),
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ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
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ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),
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ALUOps.ADDR -> ((io.op1 + io.op2) & -2.S),
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ALUOps.COPY_A -> io.op1,
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ALUOps.COPY_B -> io.op2,
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)
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@ -20,9 +20,11 @@ class EXBarrier extends MultiIOModule {
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val in = Input(new EXBarrierIO)
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val out = Output(new EXBarrierIO)
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val flush = Output(Bool())
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val branchAddr = Output(UInt(32.W))
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val branchIn = Input(Bool())
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val branchOut = Output(Bool())
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val branchAddrIn = Input(UInt(32.W))
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val branchAddrOut = Output(UInt(32.W))
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val forwardEx = Output(new Forwarding)
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})
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val delay = Reg(new EXBarrierIO)
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@ -31,5 +33,9 @@ class EXBarrier extends MultiIOModule {
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io.flush := io.branchIn
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io.branchOut := io.branchIn
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io.branchAddr := io.in.ALUResult
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io.branchAddrOut := io.branchAddrIn
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io.forwardEx.write := io.in.writeEnable
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io.forwardEx.writeAddr := io.in.writeAddr
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io.forwardEx.writeData := Mux(io.in.jump, io.in.returnAddr, io.in.ALUResult)
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}
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@ -39,9 +39,39 @@ class InstructionDecode extends MultiIOModule {
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val branchType = Output(UInt(3.W))
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val jump = Output(Bool())
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val returnAddr = Output(UInt(32.W))
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val branchAddr = Output(UInt(32.W))
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val forwardEx = Input(new Forwarding)
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val forwardMem = Input(new Forwarding)
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val forwardWb = Input(new Forwarding)
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val forwardId = Input(new Forwarding)
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}
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)
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def forward(data: UInt, addr: UInt, useForward: Bool, ex: Forwarding, mem: Forwarding, wb: Forwarding, id: Forwarding): UInt = {
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Mux(
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!useForward,
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data,
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Mux(
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ex.valid && ex.writeAddr === addr,
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ex.writeData,
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Mux(
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mem.valid && mem.writeAddr === addr,
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mem.writeData,
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Mux(
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wb.valid && wb.writeAddr === addr,
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wb.writeData,
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Mux(
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id.valid && id.writeAddr === addr,
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id.writeData,
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data,
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)
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)
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)
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)
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)
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}
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val registers = Module(new Registers)
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val decoder = Module(new Decoder).io
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@ -94,4 +124,7 @@ class InstructionDecode extends MultiIOModule {
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io.writeEnableOut := decoder.controlSignals.regWrite
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io.memRead := decoder.controlSignals.memRead
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io.memWrite := decoder.controlSignals.memWrite
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val op1 = forward(io.op1.asUInt(), io.r1Address, io.isOp1RValue, ex = io.forwardEx, mem = io.forwardMem, wb = io.forwardWb, id = io.forwardId).asSInt()
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io.branchAddr := ((op1 + io.op2) & -2.S).asUInt()
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}
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@ -13,6 +13,7 @@ class IDBarrierIO extends Bundle {
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val r2Value = UInt(32.W)
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val r2Address = UInt(5.W)
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val returnAddr = UInt(32.W)
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val branchAddr = UInt(32.W)
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val jump = Bool()
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val ALUop = UInt(4.W)
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val branchType = UInt(3.W)
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@ -119,7 +119,6 @@ object ALUOps {
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val SRA = 9.U(4.W)
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val COPY_A = 10.U(4.W)
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val COPY_B = 11.U(4.W)
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val ADDR = 12.U(4.W)
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val DC = 15.U(4.W)
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}
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