41 lines
1 KiB
Scala
41 lines
1 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.experimental.MultiIOModule
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class EXBarrierIO extends Bundle {
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val ALUResult = UInt(32.W)
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val returnAddr = UInt(32.W)
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val r2Value = UInt(32.W)
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val writeAddr = UInt(5.W)
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val writeEnable = Bool()
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val memRead = Bool()
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val memWrite = Bool()
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val jump = Bool()
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}
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class EXBarrier extends MultiIOModule {
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val io = IO(
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new Bundle {
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val in = Input(new EXBarrierIO)
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val out = Output(new EXBarrierIO)
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val flush = Output(Bool())
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val branchIn = Input(Bool())
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val branchOut = Output(Bool())
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val branchAddrIn = Input(UInt(32.W))
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val branchAddrOut = Output(UInt(32.W))
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val forwardEx = Output(new Forwarding)
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})
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val delay = Reg(new EXBarrierIO)
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delay := io.in
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io.out := delay
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io.flush := io.branchIn
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io.branchOut := io.branchIn
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io.branchAddrOut := io.branchAddrIn
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io.forwardEx.write := io.in.writeEnable
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io.forwardEx.writeAddr := io.in.writeAddr
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io.forwardEx.writeData := Mux(io.in.jump, io.in.returnAddr, io.in.ALUResult)
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}
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