package FiveStage

import chisel3._
import chisel3.experimental.MultiIOModule

class EXBarrierIO extends Bundle {
  val ALUResult = UInt(32.W)
  val returnAddr = UInt(32.W)
  val r2Value = UInt(32.W)
  val writeAddr = UInt(5.W)
  val writeEnable = Bool()
  val memRead = Bool()
  val memWrite = Bool()
  val jump = Bool()
}

class EXBarrier extends MultiIOModule {
  val io = IO(
    new Bundle {
      val in = Input(new EXBarrierIO)
      val out = Output(new EXBarrierIO)
      val flush = Output(Bool())
      val branchIn = Input(Bool())
      val branchOut = Output(Bool())
      val branchAddrIn = Input(UInt(32.W))
      val branchAddrOut = Output(UInt(32.W))
      val forwardEx = Output(new Forwarding)
    })

  val delay = Reg(new EXBarrierIO)
  delay := io.in
  io.out := delay

  io.flush := io.branchIn
  io.branchOut := io.branchIn
  io.branchAddrOut := io.branchAddrIn

  io.forwardEx.write := io.in.writeEnable
  io.forwardEx.writeAddr := io.in.writeAddr
  io.forwardEx.writeData := Mux(io.in.jump, io.in.returnAddr, io.in.ALUResult)
}