112 lines
7.2 KiB
Scala
112 lines
7.2 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.util.BitPat
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import chisel3.util.ListLookup
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/**
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* This module is mostly done, but you will have to fill in the blanks in opcodeMap.
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* You may want to add more signals to be decoded in this module depending on your
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* design if you so desire.
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*
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* In the "classic" 5 stage decoder signals such as op1select and immType
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* are not included, however I have added them to my design, and similarily you might
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* find it useful to add more
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*/
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class Decoder() extends Module {
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val io = IO(new Bundle {
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val instruction = Input(new Instruction)
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val controlSignals = Output(new ControlSignals)
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val branchType = Output(UInt(3.W))
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val op1Select = Output(UInt(1.W))
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val op2Select = Output(UInt(1.W))
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val immType = Output(UInt(3.W))
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val ALUop = Output(UInt(4.W))
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})
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import lookup._
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import Op1Select._
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import Op2Select._
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import branchType._
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import ImmFormat._
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val N = 0.asUInt(1.W)
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val Y = 1.asUInt(1.W)
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/**
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* In scala we sometimes (ab)use the `->` operator to create tuples.
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* The reason for this is that it serves as convenient sugar to make maps.
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*
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* This doesn't matter to you, just fill in the blanks in the style currently
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* used, I just want to demystify some of the scala magic.
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*
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* `a -> b` == `(a, b)` == `Tuple2(a, b)`
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*/
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val opcodeMap: Array[(BitPat, List[UInt])] = Array(
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// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
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ADD -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD ),
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SUB -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB ),
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AND -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.AND ),
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OR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.OR ),
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XOR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.XOR ),
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SLT -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLT ),
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SLTU -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLTU ),
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SRA -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRA ),
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SRL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRL ),
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SLL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLL ),
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// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
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ADDI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ),
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ANDI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.AND ),
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ORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.OR ),
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XORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.XOR ),
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SLTI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLT ),
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SLTIU -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLTU ),
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SRAI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SRA ),
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SRLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SRL ),
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SLLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLL ),
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// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
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LUI -> List(Y, N, N, N, N, branchType.DC, Op1Select.DC, imm, ImmFormat.UTYPE, ALUOps.COPY_B),
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AUIPC -> List(Y, N, N, N, N, branchType.DC, Op1Select.PC, imm, ImmFormat.UTYPE, ALUOps.ADD ),
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// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
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LW -> List(Y, Y, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ),
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SW -> List(N, N, Y, N, N, branchType.DC, rs1, imm, ImmFormat.STYPE, ALUOps.ADD ),
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// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
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BEQ -> List(N, N, N, Y, N, branchType.beq, PC, imm, ImmFormat.BTYPE, ALUOps.ADD ),
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BNE -> List(N, N, N, Y, N, branchType.neq, PC, imm, ImmFormat.BTYPE, ALUOps.ADD ),
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BLT -> List(N, N, N, Y, N, branchType.lt, PC, imm, ImmFormat.BTYPE, ALUOps.ADD ),
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BGE -> List(N, N, N, Y, N, branchType.gte, PC, imm, ImmFormat.BTYPE, ALUOps.ADD ),
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BLTU -> List(N, N, N, Y, N, branchType.ltu, PC, imm, ImmFormat.BTYPE, ALUOps.ADD ),
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BGEU -> List(N, N, N, Y, N, branchType.gteu, PC, imm, ImmFormat.BTYPE, ALUOps.ADD ),
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// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
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JAL -> List(Y, N, N, Y, Y, branchType.jump, PC, imm, ImmFormat.JTYPE, ALUOps.ADD ),
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JALR -> List(Y, N, N, Y, Y, branchType.jump, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ),
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)
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val NOP = List(N, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.DC)
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val decodedControlSignals = ListLookup(
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io.instruction.asUInt(),
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NOP,
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opcodeMap)
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io.controlSignals.regWrite := decodedControlSignals(0)
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io.controlSignals.memRead := decodedControlSignals(1)
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io.controlSignals.memWrite := decodedControlSignals(2)
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io.controlSignals.branch := decodedControlSignals(3)
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io.controlSignals.jump := decodedControlSignals(4)
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io.branchType := decodedControlSignals(5)
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io.op1Select := decodedControlSignals(6)
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io.op2Select := decodedControlSignals(7)
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io.immType := decodedControlSignals(8)
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io.ALUop := decodedControlSignals(9)
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}
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