From 3216c89dae0cc4d09e2a041a3504cffd996b1707 Mon Sep 17 00:00:00 2001 From: Sebastian Bugge Date: Tue, 12 Nov 2024 15:01:04 +0100 Subject: [PATCH] Move address calculation to ID. --- src/main/scala/CPU.scala | 10 ++++++++- src/main/scala/Decoder.scala | 2 +- src/main/scala/EX.scala | 1 - src/main/scala/EXBarrier.scala | 10 +++++++-- src/main/scala/ID.scala | 33 ++++++++++++++++++++++++++++ src/main/scala/IDBarrier.scala | 1 + src/main/scala/ToplevelSignals.scala | 1 - 7 files changed, 52 insertions(+), 6 deletions(-) diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala index d5e17c7..31530e8 100644 --- a/src/main/scala/CPU.scala +++ b/src/main/scala/CPU.scala @@ -90,6 +90,7 @@ class CPU extends MultiIOModule { IDBarrier.in.r2Address := ID.io.r2Address IDBarrier.in.ALUop := ID.io.ALUOp IDBarrier.in.returnAddr := ID.io.returnAddr + IDBarrier.in.branchAddr := ID.io.branchAddr IDBarrier.in.jump := ID.io.jump IDBarrier.in.branchType := ID.io.branchType IDBarrier.in.writeEnable := ID.io.writeEnableOut @@ -109,6 +110,7 @@ class CPU extends MultiIOModule { EXBarrier.branchIn := EX.io.branch EXBarrier.in.jump := IDBarrier.out.jump EXBarrier.in.returnAddr := IDBarrier.out.returnAddr + EXBarrier.branchAddrIn := IDBarrier.out.branchAddr EXBarrier.in.writeEnable := IDBarrier.out.writeEnable EXBarrier.in.writeAddr := IDBarrier.out.writeAddr EXBarrier.in.memWrite := IDBarrier.out.memWrite @@ -126,6 +128,12 @@ class CPU extends MultiIOModule { MEMBarrier.in.writeEnable := EXBarrier.out.writeEnable MEMBarrier.in.writeAddr := EXBarrier.out.writeAddr + // Fast branching forwarding + ID.io.forwardEx := EXBarrier.forwardEx + ID.io.forwardMem := MEMBarrier.forwardMem + ID.io.forwardWb := MEMBarrier.forwardWb + ID.io.forwardId := MEMBarrier.forwardId + // Write back ID.io.writeData := MEMBarrier.out.data ID.io.writeEnableIn := MEMBarrier.out.writeEnable @@ -133,7 +141,7 @@ class CPU extends MultiIOModule { // Branching IF.io.branch := EXBarrier.branchOut - IF.io.branchAddress := EXBarrier.branchAddr + IF.io.branchAddress := EXBarrier.branchAddrOut // Stall IF.io.stall := IDBarrier.stall diff --git a/src/main/scala/Decoder.scala b/src/main/scala/Decoder.scala index 3f6dc46..71d324b 100644 --- a/src/main/scala/Decoder.scala +++ b/src/main/scala/Decoder.scala @@ -87,7 +87,7 @@ class Decoder() extends Module { // signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp JAL -> List(Y, N, N, Y, Y, branchType.jump, PC, imm, ImmFormat.JTYPE, ALUOps.ADD ), - JALR -> List(Y, N, N, Y, Y, branchType.jump, rs1, imm, ImmFormat.ITYPE, ALUOps.ADDR ), + JALR -> List(Y, N, N, Y, Y, branchType.jump, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ), ) diff --git a/src/main/scala/EX.scala b/src/main/scala/EX.scala index a65bb61..539ae2d 100644 --- a/src/main/scala/EX.scala +++ b/src/main/scala/EX.scala @@ -31,7 +31,6 @@ class Execute extends MultiIOModule { ALUOps.SRA -> (io.op1 >> io.op2(4, 0)), ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(), ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(), - ALUOps.ADDR -> ((io.op1 + io.op2) & -2.S), ALUOps.COPY_A -> io.op1, ALUOps.COPY_B -> io.op2, ) diff --git a/src/main/scala/EXBarrier.scala b/src/main/scala/EXBarrier.scala index 5e8687e..45f933e 100644 --- a/src/main/scala/EXBarrier.scala +++ b/src/main/scala/EXBarrier.scala @@ -20,9 +20,11 @@ class EXBarrier extends MultiIOModule { val in = Input(new EXBarrierIO) val out = Output(new EXBarrierIO) val flush = Output(Bool()) - val branchAddr = Output(UInt(32.W)) val branchIn = Input(Bool()) val branchOut = Output(Bool()) + val branchAddrIn = Input(UInt(32.W)) + val branchAddrOut = Output(UInt(32.W)) + val forwardEx = Output(new Forwarding) }) val delay = Reg(new EXBarrierIO) @@ -31,5 +33,9 @@ class EXBarrier extends MultiIOModule { io.flush := io.branchIn io.branchOut := io.branchIn - io.branchAddr := io.in.ALUResult + io.branchAddrOut := io.branchAddrIn + + io.forwardEx.write := io.in.writeEnable + io.forwardEx.writeAddr := io.in.writeAddr + io.forwardEx.writeData := Mux(io.in.jump, io.in.returnAddr, io.in.ALUResult) } diff --git a/src/main/scala/ID.scala b/src/main/scala/ID.scala index 1027e70..8d39e95 100644 --- a/src/main/scala/ID.scala +++ b/src/main/scala/ID.scala @@ -39,9 +39,39 @@ class InstructionDecode extends MultiIOModule { val branchType = Output(UInt(3.W)) val jump = Output(Bool()) val returnAddr = Output(UInt(32.W)) + val branchAddr = Output(UInt(32.W)) + + val forwardEx = Input(new Forwarding) + val forwardMem = Input(new Forwarding) + val forwardWb = Input(new Forwarding) + val forwardId = Input(new Forwarding) } ) + def forward(data: UInt, addr: UInt, useForward: Bool, ex: Forwarding, mem: Forwarding, wb: Forwarding, id: Forwarding): UInt = { + Mux( + !useForward, + data, + Mux( + ex.valid && ex.writeAddr === addr, + ex.writeData, + Mux( + mem.valid && mem.writeAddr === addr, + mem.writeData, + Mux( + wb.valid && wb.writeAddr === addr, + wb.writeData, + Mux( + id.valid && id.writeAddr === addr, + id.writeData, + data, + ) + ) + ) + ) + ) + } + val registers = Module(new Registers) val decoder = Module(new Decoder).io @@ -94,4 +124,7 @@ class InstructionDecode extends MultiIOModule { io.writeEnableOut := decoder.controlSignals.regWrite io.memRead := decoder.controlSignals.memRead io.memWrite := decoder.controlSignals.memWrite + + val op1 = forward(io.op1.asUInt(), io.r1Address, io.isOp1RValue, ex = io.forwardEx, mem = io.forwardMem, wb = io.forwardWb, id = io.forwardId).asSInt() + io.branchAddr := ((op1 + io.op2) & -2.S).asUInt() } diff --git a/src/main/scala/IDBarrier.scala b/src/main/scala/IDBarrier.scala index c924233..ec5ecfc 100644 --- a/src/main/scala/IDBarrier.scala +++ b/src/main/scala/IDBarrier.scala @@ -13,6 +13,7 @@ class IDBarrierIO extends Bundle { val r2Value = UInt(32.W) val r2Address = UInt(5.W) val returnAddr = UInt(32.W) + val branchAddr = UInt(32.W) val jump = Bool() val ALUop = UInt(4.W) val branchType = UInt(3.W) diff --git a/src/main/scala/ToplevelSignals.scala b/src/main/scala/ToplevelSignals.scala index e56b572..7fe70f5 100644 --- a/src/main/scala/ToplevelSignals.scala +++ b/src/main/scala/ToplevelSignals.scala @@ -119,7 +119,6 @@ object ALUOps { val SRA = 9.U(4.W) val COPY_A = 10.U(4.W) val COPY_B = 11.U(4.W) - val ADDR = 12.U(4.W) val DC = 15.U(4.W) }