36 lines
774 B
Scala
36 lines
774 B
Scala
package FiveStage
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import chisel3._
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import chisel3.experimental.MultiIOModule
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class IFBarrier extends MultiIOModule {
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val io = IO(
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new Bundle {
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val PCin = Input(UInt(32.W))
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val PCout = Output(UInt(32.W))
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val instructionIn = Input(new Instruction)
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val instructionOut = Output(new Instruction)
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val stall = Input(Bool())
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val flush = Input(Bool())
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})
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val PC = RegInit(UInt(32.W), 0.U)
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PC := Mux(io.stall, PC, io.PCin)
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io.PCout := PC
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val instruction = Reg(new Instruction)
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val replay = RegInit(Bool(), false.B)
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replay := io.stall
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instruction := io.instructionIn
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io.instructionOut := Mux(
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io.stall || io.flush,
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Instruction.NOP,
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Mux(
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replay,
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instruction,
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io.instructionIn
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)
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)
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}
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