|
Const.scala
|
Rewrite exercise stuff
|
2019-06-07 19:54:18 +02:00 |
|
CPU.scala
|
Lower branch cycles to two.
|
2024-11-12 12:13:37 +01:00 |
|
Decoder.scala
|
Unmodify the decoder.
|
2024-10-18 09:23:47 +02:00 |
|
DMem.scala
|
Nuke
|
2019-06-07 17:43:33 +02:00 |
|
EX.scala
|
Almost working jump.
|
2024-10-04 04:11:26 +02:00 |
|
EXBarrier.scala
|
Lower branch cycles to two.
|
2024-11-12 12:13:37 +01:00 |
|
ID.scala
|
Working branching.
|
2024-11-11 17:49:10 +01:00 |
|
IDBarrier.scala
|
Do memread stalling correctly.
|
2024-11-11 01:59:20 +01:00 |
|
IF.scala
|
Add single cycle stall to branching.
|
2024-11-12 12:28:38 +01:00 |
|
IFBarrier.scala
|
Add single cycle stall to branching.
|
2024-11-12 12:28:38 +01:00 |
|
IMem.scala
|
Nuke
|
2019-06-07 17:43:33 +02:00 |
|
main.scala
|
Stuff I forgot to commit.
|
2020-06-29 16:17:24 +02:00 |
|
MEM.scala
|
Fix mem-read sync.
|
2024-11-01 00:15:41 +01:00 |
|
MEMBarrier.scala
|
Simplify MEMBarrier.
|
2024-11-08 01:47:20 +01:00 |
|
Registers.scala
|
Nuke
|
2019-06-07 17:43:33 +02:00 |
|
SetupSignals.scala
|
Nuke
|
2019-06-07 17:43:33 +02:00 |
|
Tile.scala
|
Nuke
|
2019-06-07 17:43:33 +02:00 |
|
ToplevelSignals.scala
|
Almost working jump.
|
2024-10-04 04:11:26 +02:00 |
