40 commits

Author	SHA1	Message	Date
Sebastian Bugge	e0b6634a93	Add single cycle stall to branching.	2024-11-12 12:28:38 +01:00
Sebastian Bugge	9e12c60d27	Lower branch cycles to two.	2024-11-12 12:13:37 +01:00
Sebastian Bugge	cfce1b6b54	Working branching.	2024-11-11 17:49:10 +01:00
Sebastian Bugge	23656db068	Do memread stalling correctly.	2024-11-11 01:59:20 +01:00
Sebastian Bugge	4cfd8268fd	Simplify MEMBarrier.	2024-11-08 01:47:20 +01:00
Sebastian Bugge	9192d576e7	Simplify IDBarrier.	2024-11-08 01:30:51 +01:00
Sebastian Bugge	42d77a0d85	Simplify EXBarrier.	2024-11-08 01:06:07 +01:00
Sebastian Bugge	6d6474530c	Simplify IDBarrier.	2024-11-07 23:51:17 +01:00
Sebastian Bugge	1eefeca2d6	Simplify forwarding.	2024-11-05 14:13:15 +01:00
Sebastian Bugge	804e1ed2e6	It works!	2024-11-01 03:32:59 +01:00
Sebastian Bugge	800e7b6eb0	Rewrite stall to be more modular.	2024-11-01 03:13:00 +01:00
Sebastian Bugge	97b13a813f	Actually fix forwarding.	2024-11-01 03:02:36 +01:00
Sebastian Bugge	4c684f1718	Fix mem-read sync.	2024-11-01 00:15:41 +01:00
Sebastian Bugge	af2cc43540	Add MEMbarrier.	2024-11-01 00:02:37 +01:00
Sebastian Bugge	b25cd420e8	Unmodify the decoder.	2024-10-18 09:23:47 +02:00
Sebastian Bugge	1d433dd791	Add stall.	2024-10-18 08:20:40 +02:00
Sebastian Bugge	bcbe07b601	Working forwarding (i think).	2024-10-18 07:53:22 +02:00
Sebastian Bugge	f2964c280c	Properly parse NOP.	2024-10-18 07:07:29 +02:00
Sebastian Bugge	7b633f2a75	Fix jump!	2024-10-10 00:04:18 +02:00
Sebastian Bugge	323e373d0e	Almost working jump.	2024-10-04 04:11:26 +02:00
Sebastian Bugge	92d0dfd9eb	Working branching.	2024-10-04 02:16:17 +02:00
Sebastian Bugge	934593fb6f	Use copy ALU OPs.	2024-10-03 14:40:30 +02:00
Sebastian Bugge	e09a358320	Use MUX instead of when.	2024-09-27 08:49:36 +02:00
Sebastian Bugge	abef04fc22	LUI working.	2024-09-27 08:42:43 +02:00
Sebastian Bugge	a48c9a1ba8	Working SLT	2024-09-27 08:31:56 +02:00
Sebastian Bugge	39a6c5f87e	Working store and load.	2024-09-27 08:14:15 +02:00
Sebastian Bugge	f7c93b1292	Half-working load.	2024-09-27 07:51:25 +02:00
Sebastian Bugge	961ae49523	Add working 4real.	2024-09-27 04:47:26 +02:00
Sebastian Bugge	44ccf12cad	Working adder.	2024-09-27 04:22:10 +02:00
David Metz	39c008567d	remove aliasing for branchType and fix tests ending in dependent load chains	2023-08-18 14:57:56 +02:00
peteraa	2e37f0b8d7	Merge branch 'master' of https://github.com/PeterAaser/TDT4255_EX2	2020-06-29 16:19:56 +02:00
peteraa	9f47433501	Stuff I forgot to commit.	2020-06-29 16:17:24 +02:00
peteraaser	8dc92fb8e1	Remove MemToReg. ... Pretty sure MemToReg is a MIPS relic, it is redundant so long as all memory reads are put into registers.	2020-06-02 14:58:06 +02:00
peteraaser	3b635be2dc	Github render test	2020-06-01 14:16:08 +02:00
peteraa	8bb3c892a1	Beef up add walkthrough	2019-09-05 14:37:33 +02:00
peteraa	27b7c0556e	Simplify NOP and bubble logic.	2019-09-05 14:09:05 +02:00
peteraa	8e2d686b5c	Add special handlers for shift instructions.	2019-09-04 11:52:49 +02:00
peteraa	8982b5529c	Clarify setup instructions for IF.scala	2019-08-28 16:13:15 +02:00
peteraa	f5d038eaf6	Rewrite exercise stuff	2019-06-07 19:54:18 +02:00
peteraa	932413bb3d	Nuke	2019-06-07 17:43:33 +02:00