Simplify IDBarrier.
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2EFFEDEE03519691
2 changed files with 52 additions and 123 deletions
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@ -80,39 +80,39 @@ class CPU extends MultiIOModule {
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ID.io.instruction := IFBarrier.instructionOut
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ID.io.pc := IFBarrier.PCout
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IDBarrier.op1in := ID.io.op1
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IDBarrier.op2in := ID.io.op2
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IDBarrier.isOp1RValueIn := ID.io.isOp1RValue
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IDBarrier.isOp2RValueIn := ID.io.isOp2RValue
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IDBarrier.r1ValueIn := ID.io.r1Value
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IDBarrier.r2ValueIn := ID.io.r2Value
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IDBarrier.r1AddressIn := ID.io.r1Address
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IDBarrier.r2AddressIn := ID.io.r2Address
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IDBarrier.ALUopIn := ID.io.ALUOp
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IDBarrier.returnAddrIn := ID.io.returnAddr
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IDBarrier.jumpIn := ID.io.jump
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IDBarrier.branchTypeIn := ID.io.branchType
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IDBarrier.writeEnableIn := ID.io.writeEnableOut
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IDBarrier.writeAddrIn := ID.io.writeAddrOut
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IDBarrier.memWriteIn := ID.io.memWrite
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IDBarrier.memReadIn := ID.io.memRead
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IDBarrier.in.op1 := ID.io.op1
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IDBarrier.in.op2 := ID.io.op2
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IDBarrier.in.isOp1RValue := ID.io.isOp1RValue
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IDBarrier.in.isOp2RValue := ID.io.isOp2RValue
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IDBarrier.in.r1Value := ID.io.r1Value
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IDBarrier.in.r2Value := ID.io.r2Value
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IDBarrier.in.r1Address := ID.io.r1Address
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IDBarrier.in.r2Address := ID.io.r2Address
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IDBarrier.in.ALUop := ID.io.ALUOp
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IDBarrier.in.returnAddr := ID.io.returnAddr
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IDBarrier.in.jump := ID.io.jump
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IDBarrier.in.branchType := ID.io.branchType
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IDBarrier.in.writeEnable := ID.io.writeEnableOut
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IDBarrier.in.writeAddr := ID.io.writeAddrOut
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IDBarrier.in.memWrite := ID.io.memWrite
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IDBarrier.in.memRead := ID.io.memRead
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EX.io.op1 := forward(IDBarrier.op1out.asUInt(), IDBarrier.r1AddressOut, IDBarrier.isOp1RValueOut, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EX.io.op2 := forward(IDBarrier.op2out.asUInt(), IDBarrier.r2AddressOut, IDBarrier.isOp2RValueOut, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EX.io.ALUOp := IDBarrier.ALUopOut
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EX.io.branchType := IDBarrier.branchTypeOut
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EX.io.rs1ValueIn := forward(IDBarrier.r1ValueOut, IDBarrier.r1AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EX.io.rs2ValueIn := forward(IDBarrier.r2ValueOut, IDBarrier.r2AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EX.io.op1 := forward(IDBarrier.out.op1.asUInt(), IDBarrier.out.r1Address, IDBarrier.out.isOp1RValue, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EX.io.op2 := forward(IDBarrier.out.op2.asUInt(), IDBarrier.out.r2Address, IDBarrier.out.isOp2RValue, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EX.io.ALUOp := IDBarrier.out.ALUop
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EX.io.branchType := IDBarrier.out.branchType
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EX.io.rs1ValueIn := forward(IDBarrier.out.r1Value, IDBarrier.out.r1Address, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EX.io.rs2ValueIn := forward(IDBarrier.out.r2Value, IDBarrier.out.r2Address, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
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EXBarrier.in.r2Value := EX.io.rs2ValueOut.asUInt()
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EXBarrier.in.ALUResult := EX.io.ALUResult.asUInt()
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EXBarrier.in.branch := EX.io.branch
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EXBarrier.in.jump := IDBarrier.jumpOut
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EXBarrier.in.returnAddr := IDBarrier.returnAddrOut
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EXBarrier.in.writeEnable := IDBarrier.writeEnableOut
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EXBarrier.in.writeAddr := IDBarrier.writeAddrOut
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EXBarrier.in.memWrite := IDBarrier.memWriteOut
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EXBarrier.in.memRead := IDBarrier.memReadOut
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EXBarrier.in.jump := IDBarrier.out.jump
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EXBarrier.in.returnAddr := IDBarrier.out.returnAddr
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EXBarrier.in.writeEnable := IDBarrier.out.writeEnable
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EXBarrier.in.writeAddr := IDBarrier.out.writeAddr
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EXBarrier.in.memWrite := IDBarrier.out.memWrite
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EXBarrier.in.memRead := IDBarrier.out.memRead
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MEM.io.ALUResult := EXBarrier.out.ALUResult
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MEM.io.jump := EXBarrier.out.jump
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@ -3,104 +3,33 @@ package FiveStage
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import chisel3._
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import chisel3.experimental.MultiIOModule
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class IDBarrierIO extends Bundle {
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val op1 = SInt(32.W)
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val isOp1RValue = Bool()
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val op2 = SInt(32.W)
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val isOp2RValue = Bool()
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val r1Value = UInt(32.W)
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val r1Address = UInt(5.W)
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val r2Value = UInt(32.W)
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val r2Address = UInt(5.W)
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val returnAddr = UInt(32.W)
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val jump = Bool()
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val ALUop = UInt(4.W)
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val branchType = UInt(3.W)
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val writeAddr = UInt(5.W)
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val writeEnable = Bool()
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val memRead = Bool()
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val memWrite = Bool()
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}
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class IDBarrier extends MultiIOModule {
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val io = IO(
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new Bundle {
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val op1in = Input(SInt(32.W))
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val op1out = Output(SInt(32.W))
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val isOp1RValueIn = Input(Bool())
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val isOp1RValueOut = Output(Bool())
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val op2in = Input(SInt(32.W))
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val op2out = Output(SInt(32.W))
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val isOp2RValueIn = Input(Bool())
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val isOp2RValueOut = Output(Bool())
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val r1ValueIn = Input(UInt(32.W))
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val r1ValueOut = Output(UInt(32.W))
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val r1AddressIn = Input(UInt(5.W))
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val r1AddressOut = Output(UInt(5.W))
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val r2ValueIn = Input(UInt(32.W))
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val r2ValueOut = Output(UInt(32.W))
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val r2AddressIn = Input(UInt(5.W))
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val r2AddressOut = Output(UInt(5.W))
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val returnAddrIn = Input(UInt(32.W))
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val returnAddrOut = Output(UInt(32.W))
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val jumpIn = Input(Bool())
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val jumpOut = Output(Bool())
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val ALUopIn = Input(UInt(4.W))
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val ALUopOut = Output(UInt(4.W))
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val branchTypeIn = Input(UInt(3.W))
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val branchTypeOut = Output(UInt(3.W))
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val writeAddrIn = Input(UInt(5.W))
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val writeAddrOut = Output(UInt(5.W))
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val writeEnableIn = Input(Bool())
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val writeEnableOut = Output(Bool())
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val memReadIn = Input(Bool())
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val memReadOut = Output(Bool())
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val memWriteIn = Input(Bool())
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val memWriteOut = Output(Bool())
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val in = Input(new IDBarrierIO)
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val out = Output(new IDBarrierIO)
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})
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val isOp1RValue = RegInit(Bool(), false.B)
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isOp1RValue := io.isOp1RValueIn
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io.isOp1RValueOut := isOp1RValue
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val isOp2RValue = RegInit(Bool(), false.B)
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isOp2RValue := io.isOp2RValueIn
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io.isOp2RValueOut := isOp2RValue
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val r2Address = RegInit(UInt(5.W), 0.U)
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r2Address := io.r2AddressIn
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io.r2AddressOut := r2Address
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val r1Address = RegInit(UInt(5.W), 0.U)
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r1Address := io.r1AddressIn
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io.r1AddressOut := r1Address
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val op1 = RegInit(SInt(32.W), 0.S)
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op1 := io.op1in
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io.op1out := op1
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val op2 = RegInit(SInt(32.W), 0.S)
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op2 := io.op2in
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io.op2out := op2
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val r1Value = RegInit(UInt(32.W), 0.U)
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r1Value := io.r1ValueIn
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io.r1ValueOut := r1Value
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val r2Value = RegInit(UInt(32.W), 0.U)
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r2Value := io.r2ValueIn
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io.r2ValueOut := r2Value
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val returnAddr = RegInit(UInt(32.W), 0.U)
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returnAddr := io.returnAddrIn
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io.returnAddrOut := returnAddr
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val jump = RegInit(UInt(32.W), 0.U)
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jump := io.jumpIn
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io.jumpOut := jump
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val ALUop = RegInit(UInt(4.W), 0.U)
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ALUop := io.ALUopIn
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io.ALUopOut := ALUop
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val branchType = RegInit(UInt(5.W), 0.U)
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branchType := io.branchTypeIn
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io.branchTypeOut := branchType
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val writeAddr = RegInit(UInt(5.W), 0.U)
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writeAddr := io.writeAddrIn
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io.writeAddrOut := writeAddr
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val writeEnable = RegInit(Bool(), false.B)
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writeEnable := io.writeEnableIn
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io.writeEnableOut := writeEnable
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val memRead = RegInit(Bool(), false.B)
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memRead := io.memReadIn
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io.memReadOut := memRead
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val memWrite = RegInit(Bool(), false.B)
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memWrite := io.memWriteIn
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io.memWriteOut := memWrite
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val delay = Reg(new IDBarrierIO)
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delay := io.in
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io.out := delay
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}
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