From 9192d576e77da4f62ba93e457c20f7e73dcae569 Mon Sep 17 00:00:00 2001 From: Sebastian Bugge Date: Fri, 8 Nov 2024 01:30:51 +0100 Subject: [PATCH] Simplify IDBarrier. --- src/main/scala/CPU.scala | 56 ++++++++-------- src/main/scala/IDBarrier.scala | 119 +++++++-------------------------- 2 files changed, 52 insertions(+), 123 deletions(-) diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala index 8804a34..2a32b65 100644 --- a/src/main/scala/CPU.scala +++ b/src/main/scala/CPU.scala @@ -80,39 +80,39 @@ class CPU extends MultiIOModule { ID.io.instruction := IFBarrier.instructionOut ID.io.pc := IFBarrier.PCout - IDBarrier.op1in := ID.io.op1 - IDBarrier.op2in := ID.io.op2 - IDBarrier.isOp1RValueIn := ID.io.isOp1RValue - IDBarrier.isOp2RValueIn := ID.io.isOp2RValue - IDBarrier.r1ValueIn := ID.io.r1Value - IDBarrier.r2ValueIn := ID.io.r2Value - IDBarrier.r1AddressIn := ID.io.r1Address - IDBarrier.r2AddressIn := ID.io.r2Address - IDBarrier.ALUopIn := ID.io.ALUOp - IDBarrier.returnAddrIn := ID.io.returnAddr - IDBarrier.jumpIn := ID.io.jump - IDBarrier.branchTypeIn := ID.io.branchType - IDBarrier.writeEnableIn := ID.io.writeEnableOut - IDBarrier.writeAddrIn := ID.io.writeAddrOut - IDBarrier.memWriteIn := ID.io.memWrite - IDBarrier.memReadIn := ID.io.memRead + IDBarrier.in.op1 := ID.io.op1 + IDBarrier.in.op2 := ID.io.op2 + IDBarrier.in.isOp1RValue := ID.io.isOp1RValue + IDBarrier.in.isOp2RValue := ID.io.isOp2RValue + IDBarrier.in.r1Value := ID.io.r1Value + IDBarrier.in.r2Value := ID.io.r2Value + IDBarrier.in.r1Address := ID.io.r1Address + IDBarrier.in.r2Address := ID.io.r2Address + IDBarrier.in.ALUop := ID.io.ALUOp + IDBarrier.in.returnAddr := ID.io.returnAddr + IDBarrier.in.jump := ID.io.jump + IDBarrier.in.branchType := ID.io.branchType + IDBarrier.in.writeEnable := ID.io.writeEnableOut + IDBarrier.in.writeAddr := ID.io.writeAddrOut + IDBarrier.in.memWrite := ID.io.memWrite + IDBarrier.in.memRead := ID.io.memRead - EX.io.op1 := forward(IDBarrier.op1out.asUInt(), IDBarrier.r1AddressOut, IDBarrier.isOp1RValueOut, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt() - EX.io.op2 := forward(IDBarrier.op2out.asUInt(), IDBarrier.r2AddressOut, IDBarrier.isOp2RValueOut, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt() - EX.io.ALUOp := IDBarrier.ALUopOut - EX.io.branchType := IDBarrier.branchTypeOut - EX.io.rs1ValueIn := forward(IDBarrier.r1ValueOut, IDBarrier.r1AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt() - EX.io.rs2ValueIn := forward(IDBarrier.r2ValueOut, IDBarrier.r2AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt() + EX.io.op1 := forward(IDBarrier.out.op1.asUInt(), IDBarrier.out.r1Address, IDBarrier.out.isOp1RValue, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt() + EX.io.op2 := forward(IDBarrier.out.op2.asUInt(), IDBarrier.out.r2Address, IDBarrier.out.isOp2RValue, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt() + EX.io.ALUOp := IDBarrier.out.ALUop + EX.io.branchType := IDBarrier.out.branchType + EX.io.rs1ValueIn := forward(IDBarrier.out.r1Value, IDBarrier.out.r1Address, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt() + EX.io.rs2ValueIn := forward(IDBarrier.out.r2Value, IDBarrier.out.r2Address, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt() EXBarrier.in.r2Value := EX.io.rs2ValueOut.asUInt() EXBarrier.in.ALUResult := EX.io.ALUResult.asUInt() EXBarrier.in.branch := EX.io.branch - EXBarrier.in.jump := IDBarrier.jumpOut - EXBarrier.in.returnAddr := IDBarrier.returnAddrOut - EXBarrier.in.writeEnable := IDBarrier.writeEnableOut - EXBarrier.in.writeAddr := IDBarrier.writeAddrOut - EXBarrier.in.memWrite := IDBarrier.memWriteOut - EXBarrier.in.memRead := IDBarrier.memReadOut + EXBarrier.in.jump := IDBarrier.out.jump + EXBarrier.in.returnAddr := IDBarrier.out.returnAddr + EXBarrier.in.writeEnable := IDBarrier.out.writeEnable + EXBarrier.in.writeAddr := IDBarrier.out.writeAddr + EXBarrier.in.memWrite := IDBarrier.out.memWrite + EXBarrier.in.memRead := IDBarrier.out.memRead MEM.io.ALUResult := EXBarrier.out.ALUResult MEM.io.jump := EXBarrier.out.jump diff --git a/src/main/scala/IDBarrier.scala b/src/main/scala/IDBarrier.scala index 26869d4..105ca34 100644 --- a/src/main/scala/IDBarrier.scala +++ b/src/main/scala/IDBarrier.scala @@ -3,104 +3,33 @@ package FiveStage import chisel3._ import chisel3.experimental.MultiIOModule +class IDBarrierIO extends Bundle { + val op1 = SInt(32.W) + val isOp1RValue = Bool() + val op2 = SInt(32.W) + val isOp2RValue = Bool() + val r1Value = UInt(32.W) + val r1Address = UInt(5.W) + val r2Value = UInt(32.W) + val r2Address = UInt(5.W) + val returnAddr = UInt(32.W) + val jump = Bool() + val ALUop = UInt(4.W) + val branchType = UInt(3.W) + val writeAddr = UInt(5.W) + val writeEnable = Bool() + val memRead = Bool() + val memWrite = Bool() +} + class IDBarrier extends MultiIOModule { val io = IO( new Bundle { - val op1in = Input(SInt(32.W)) - val op1out = Output(SInt(32.W)) - val isOp1RValueIn = Input(Bool()) - val isOp1RValueOut = Output(Bool()) - val op2in = Input(SInt(32.W)) - val op2out = Output(SInt(32.W)) - val isOp2RValueIn = Input(Bool()) - val isOp2RValueOut = Output(Bool()) - val r1ValueIn = Input(UInt(32.W)) - val r1ValueOut = Output(UInt(32.W)) - val r1AddressIn = Input(UInt(5.W)) - val r1AddressOut = Output(UInt(5.W)) - val r2ValueIn = Input(UInt(32.W)) - val r2ValueOut = Output(UInt(32.W)) - val r2AddressIn = Input(UInt(5.W)) - val r2AddressOut = Output(UInt(5.W)) - val returnAddrIn = Input(UInt(32.W)) - val returnAddrOut = Output(UInt(32.W)) - val jumpIn = Input(Bool()) - val jumpOut = Output(Bool()) - val ALUopIn = Input(UInt(4.W)) - val ALUopOut = Output(UInt(4.W)) - val branchTypeIn = Input(UInt(3.W)) - val branchTypeOut = Output(UInt(3.W)) - val writeAddrIn = Input(UInt(5.W)) - val writeAddrOut = Output(UInt(5.W)) - val writeEnableIn = Input(Bool()) - val writeEnableOut = Output(Bool()) - val memReadIn = Input(Bool()) - val memReadOut = Output(Bool()) - val memWriteIn = Input(Bool()) - val memWriteOut = Output(Bool()) + val in = Input(new IDBarrierIO) + val out = Output(new IDBarrierIO) }) - val isOp1RValue = RegInit(Bool(), false.B) - isOp1RValue := io.isOp1RValueIn - io.isOp1RValueOut := isOp1RValue - - val isOp2RValue = RegInit(Bool(), false.B) - isOp2RValue := io.isOp2RValueIn - io.isOp2RValueOut := isOp2RValue - - val r2Address = RegInit(UInt(5.W), 0.U) - r2Address := io.r2AddressIn - io.r2AddressOut := r2Address - - val r1Address = RegInit(UInt(5.W), 0.U) - r1Address := io.r1AddressIn - io.r1AddressOut := r1Address - - val op1 = RegInit(SInt(32.W), 0.S) - op1 := io.op1in - io.op1out := op1 - - val op2 = RegInit(SInt(32.W), 0.S) - op2 := io.op2in - io.op2out := op2 - - val r1Value = RegInit(UInt(32.W), 0.U) - r1Value := io.r1ValueIn - io.r1ValueOut := r1Value - - val r2Value = RegInit(UInt(32.W), 0.U) - r2Value := io.r2ValueIn - io.r2ValueOut := r2Value - - val returnAddr = RegInit(UInt(32.W), 0.U) - returnAddr := io.returnAddrIn - io.returnAddrOut := returnAddr - - val jump = RegInit(UInt(32.W), 0.U) - jump := io.jumpIn - io.jumpOut := jump - - val ALUop = RegInit(UInt(4.W), 0.U) - ALUop := io.ALUopIn - io.ALUopOut := ALUop - - val branchType = RegInit(UInt(5.W), 0.U) - branchType := io.branchTypeIn - io.branchTypeOut := branchType - - val writeAddr = RegInit(UInt(5.W), 0.U) - writeAddr := io.writeAddrIn - io.writeAddrOut := writeAddr - - val writeEnable = RegInit(Bool(), false.B) - writeEnable := io.writeEnableIn - io.writeEnableOut := writeEnable - - val memRead = RegInit(Bool(), false.B) - memRead := io.memReadIn - io.memReadOut := memRead - - val memWrite = RegInit(Bool(), false.B) - memWrite := io.memWriteIn - io.memWriteOut := memWrite + val delay = Reg(new IDBarrierIO) + delay := io.in + io.out := delay }