package FiveStage

import chisel3._
import chisel3.experimental.MultiIOModule

class IFBarrier extends MultiIOModule {
  val io = IO(
    new Bundle {
      val PCin = Input(UInt(32.W))
      val PCout = Output(UInt(32.W))
      val instructionIn = Input(new Instruction)
      val instructionOut = Output(new Instruction)
      val stall = Input(Bool())
      val flush = Input(Bool())
    })

  val PC = RegInit(UInt(32.W), 0.U)
  PC := Mux(io.stall, PC, io.PCin)
  io.PCout := PC

  val instruction = Reg(new Instruction)
  val replay = RegInit(Bool(), false.B)

  replay := io.stall
  instruction := io.instructionIn

  io.instructionOut := Mux(
    io.stall || io.flush,
    Instruction.NOP,
    Mux(
      replay,
      instruction,
      io.instructionIn
    )
  )
}