66 lines
3.1 KiB
Org Mode
66 lines
3.1 KiB
Org Mode
Best viewed in emacs org mode.
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This is the coursework for the graded part of the TDT4255 course at NTNU.
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* Instructions
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#+ATTR_HTML: title="Join the chat at https://gitter.im/RISCV-FiveStage/community"
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[[https://gitter.im/RISCV-FiveStage/community?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge][file:https://badges.gitter.im/RISCV-FiveStage/community.svg]]
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To get started with designing your 5-stage RISC-V pipeline you should follow the
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[[./exercise.org][Exercise instructions]]
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If you want an introduction to chisel and hardware design you should do the [[https://github.com/PeterAaser/tdt4255-chisel-intro][Chisel Intro]]
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exercise first.
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* About
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Since much of the tooling for HW design is rather difficult to work with this skeleton comes
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with a lot of reinvented wheels which should make inspecting what is really going on a little
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clearer.
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The FiveStage suite works in the following way:
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** Parsing a test
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The [[./src/test/scala/RISCV/Parser.scala][Parser]] parses an assembly test found in the test resource directory.
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The resulting program can then be loaded on to a VM, or assembled into machine code.
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** Interpreting the test
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Next the parsed assembly code is run on a virtual machine.
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Relevant information is then compiled in an execution trace log which shows which instruction was
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performed at a given step and what the resulting state was.
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** Preparing your circuit
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Next up the chisel design is synthesized into a circuit emulator.
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The (relatively seamless) test harness provided for your circuit is then used in order to preload
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the instruction memory with the assembled machinecode, as well as test defined initial memory and
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register configurations.
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** Running your circuit
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As with the VM, your circuit will leave an extensive log which is parsed and used to verify the
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correctness of your design
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** Checking the result
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If your processor performed the same updates to registers and memory, and terminated at the same
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address the test is successful.
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** Debugging a failed test
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When a test fails, (or if you have enabled verbose logging) a side by side execution log is shown,
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allowing you to pinpoint exactly how your processor went wrong.
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* Intended use
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This coursework is intended to be used!
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If you are a tutor currently teaching computer architecture you may freely use this project, but
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I would be very grateful if you provided me with feedback. Pull requests always welcome!
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* Contributing
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Considering the very significant amount of work saved on making your own coursework, you could
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maybe help adding features.
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Take a look at [[./TODO.org][the TODO file]] (does not render well in github) to get an idea of nice features to
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have, or add different features altogether!
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Additionally, if you write your own tests, please send a pull request! The more tests the better!
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* Solution
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This is a graded coursework, so I would prefer that if you fork this project you keep the solution
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private.
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If you want access to the solution please send me a message verifying that you are a tutor and I
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will make it available to you.
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