31 lines
1.7 KiB
Markdown
31 lines
1.7 KiB
Markdown
This is the coursework for the graded part of the TDT4255 course at NTNU.
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Since it is the authors opinion that most tools out there are vastly underdesigned, this project comes
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with a lot of added homegrown utilities, including a RISC-V parser, assembler and interpreter.
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When you test a design with a given program, that program is first parsed, then run in a software interpreter
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to get correct output, then assembled into a binary.
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This binary will then be loaded to your synthesized design (your processor) by the test harness provided in
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the skeleton code, along with any initial state.
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Your processor will run the supplied binary, and the changes to state (memory and registers) will be recorded
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and compared with the interpreter log.
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If it matches, your processor works, if not, you get an execution trace, hopefully showing what went wrong and
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where.
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To get started, read the exercise.org file, it goes over the first pieces of the puzzle.
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If you want to learn chisel on your own and use this project please send me some feedback on what you liked,
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disliked and what could have been improved :)
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If you end up using it for a course you're teaching I would be thrilled too.
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In this case, you can spend the time you're saving by sending a pull requests with some improvements!
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Pull requests are more than welcome!
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Nice to have list:
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* More sophisticated test feedback. A detailed error report on why the processor design failed.
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* Scaffolding to run synthesized designs. Preferrably targeting the PYNQ platform.
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* A fix for whatever problems *you* run into when using this project.
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* Either a battery of tests to find corner cases stress testing forwarders, hazard detectors etc, or even better, the tools to generate code with hazards automatically.
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