64 lines
1.7 KiB
Scala
64 lines
1.7 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.experimental.MultiIOModule
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class EXBarrier extends MultiIOModule {
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val io = IO(
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new Bundle {
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val ALUResultIn = Input(UInt(32.W))
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val ALUResultOut = Output(UInt(32.W))
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val returnAddrIn = Input(UInt(32.W))
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val returnAddrOut = Output(UInt(32.W))
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val r2ValueIn = Input(UInt(32.W))
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val r2ValueOut = Output(UInt(32.W))
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val writeAddrIn = Input(UInt(5.W))
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val writeAddrOut = Output(UInt(5.W))
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val writeEnableIn = Input(Bool())
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val writeEnableOut = Output(Bool())
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val memReadIn = Input(Bool())
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val memReadOut = Output(Bool())
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val memWriteIn = Input(Bool())
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val memWriteOut = Output(Bool())
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val branchIn = Input(Bool())
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val branchOut = Output(Bool())
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val jumpIn = Input(Bool())
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val jumpOut = Output(Bool())
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})
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val ALUResult = RegInit(UInt(32.W), 0.U)
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ALUResult := io.ALUResultIn
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io.ALUResultOut := ALUResult
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val returnAddr = RegInit(UInt(32.W), 0.U)
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returnAddr := io.returnAddrIn
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io.returnAddrOut := returnAddr
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val r2Value = RegInit(UInt(32.W), 0.U)
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r2Value := io.r2ValueIn
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io.r2ValueOut := r2Value
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val writeAddr = RegInit(UInt(5.W), 0.U)
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writeAddr := io.writeAddrIn
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io.writeAddrOut := writeAddr
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val writeEnable = RegInit(Bool(), false.B)
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writeEnable := io.writeEnableIn
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io.writeEnableOut := writeEnable
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val memRead = RegInit(Bool(), false.B)
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memRead := io.memReadIn
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io.memReadOut := memRead
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val memWrite = RegInit(Bool(), false.B)
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memWrite := io.memWriteIn
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io.memWriteOut := memWrite
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val branch = RegInit(Bool(), false.B)
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branch := io.branchIn
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io.branchOut := branch
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val jump = RegInit(Bool(), false.B)
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jump := io.jumpIn
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io.jumpOut := jump
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}
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