package FiveStage

import chisel3._
import chisel3.experimental.MultiIOModule

class EXBarrier extends MultiIOModule {
  val io = IO(
    new Bundle {
      val ALUResultIn = Input(UInt(32.W))
      val ALUResultOut = Output(UInt(32.W))
      val returnAddrIn = Input(UInt(32.W))
      val returnAddrOut = Output(UInt(32.W))
      val r2ValueIn = Input(UInt(32.W))
      val r2ValueOut = Output(UInt(32.W))
      val writeAddrIn = Input(UInt(5.W))
      val writeAddrOut = Output(UInt(5.W))
      val writeEnableIn = Input(Bool())
      val writeEnableOut = Output(Bool())
      val memReadIn = Input(Bool())
      val memReadOut = Output(Bool())
      val memWriteIn = Input(Bool())
      val memWriteOut = Output(Bool())
      val branchIn = Input(Bool())
      val branchOut = Output(Bool())
      val jumpIn = Input(Bool())
      val jumpOut = Output(Bool())
    })

  val ALUResult = RegInit(UInt(32.W), 0.U)
  ALUResult := io.ALUResultIn
  io.ALUResultOut := ALUResult

  val returnAddr = RegInit(UInt(32.W), 0.U)
  returnAddr := io.returnAddrIn
  io.returnAddrOut := returnAddr

  val r2Value = RegInit(UInt(32.W), 0.U)
  r2Value := io.r2ValueIn
  io.r2ValueOut := r2Value

  val writeAddr = RegInit(UInt(5.W), 0.U)
  writeAddr := io.writeAddrIn
  io.writeAddrOut := writeAddr

  val writeEnable = RegInit(Bool(), false.B)
  writeEnable := io.writeEnableIn
  io.writeEnableOut := writeEnable

  val memRead = RegInit(Bool(), false.B)
  memRead := io.memReadIn
  io.memReadOut := memRead

  val memWrite = RegInit(Bool(), false.B)
  memWrite := io.memWriteIn
  io.memWriteOut := memWrite

  val branch = RegInit(Bool(), false.B)
  branch := io.branchIn
  io.branchOut := branch

  val jump = RegInit(Bool(), false.B)
  jump := io.jumpIn
  io.jumpOut := jump
}