37 lines
824 B
Scala
37 lines
824 B
Scala
package FiveStage
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import chisel3._
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import chisel3.experimental.MultiIOModule
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class IDBarrierIO extends Bundle {
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val op1 = SInt(32.W)
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val isOp1RValue = Bool()
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val op2 = SInt(32.W)
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val isOp2RValue = Bool()
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val r1Value = UInt(32.W)
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val r1Address = UInt(5.W)
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val r2Value = UInt(32.W)
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val r2Address = UInt(5.W)
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val returnAddr = UInt(32.W)
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val jump = Bool()
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val ALUop = UInt(4.W)
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val branchType = UInt(3.W)
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val writeAddr = UInt(5.W)
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val writeEnable = Bool()
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val memRead = Bool()
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val memWrite = Bool()
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}
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class IDBarrier extends MultiIOModule {
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val io = IO(
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new Bundle {
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val in = Input(new IDBarrierIO)
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val out = Output(new IDBarrierIO)
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val stall = Output(Bool())
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})
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val delay = Reg(new IDBarrierIO)
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delay := io.in
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io.out := delay
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io.stall := io.out.memRead
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}
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