package FiveStage

import chisel3._
import chisel3.experimental.MultiIOModule

class IDBarrierIO extends Bundle {
  val op1 = SInt(32.W)
  val isOp1RValue = Bool()
  val op2 = SInt(32.W)
  val isOp2RValue = Bool()
  val r1Value = UInt(32.W)
  val r1Address = UInt(5.W)
  val r2Value = UInt(32.W)
  val r2Address = UInt(5.W)
  val returnAddr = UInt(32.W)
  val jump = Bool()
  val ALUop = UInt(4.W)
  val branchType = UInt(3.W)
  val writeAddr = UInt(5.W)
  val writeEnable = Bool()
  val memRead = Bool()
  val memWrite = Bool()
}

class IDBarrier extends MultiIOModule {
  val io = IO(
    new Bundle {
      val in = Input(new IDBarrierIO)
      val out = Output(new IDBarrierIO)
      val stall = Output(Bool())
    })

  val delay = Reg(new IDBarrierIO)
  delay := io.in
  io.out := delay
  io.stall := io.out.memRead
}