kaholaz/TDT4255
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Fix hex | int parse issue. Correctly handle li

Browse source
This commit is contained in:
peteraa 2019-09-06 14:44:01 +02:00
parent 2f2f20c075
commit ae995a7b55
2 changed files with 24 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

13
src/test/scala/RISCV/DataTypes.scala
View file

@ -158,12 +158,13 @@ object Data {
rightShifted rightShifted
} }
def splitLoHi(loBits: Int): (Int, Int) = { def splitHiLo(hiBits: Int): (Int, Int) = {
val hiBits = 32 - loBits val loBits = 32 - hiBits
val sep = 31 - loBits val sep = 31 - hiBits
val lo = i.field(31, loBits) val hi = i.field(31, hiBits)
val hi = i.field(sep, hiBits) val lo = i.field(sep, loBits)
(lo, hi) say(s"split lo hi for $i with $hiBits high bits and got low: $lo, high: $hi")
(hi, lo)
} }
def log2: Int = math.ceil(math.log(i.toDouble)/math.log(2.0)).toInt def log2: Int = math.ceil(math.log(i.toDouble)/math.log(2.0)).toInt

32
src/test/scala/RISCV/Parser.scala
View file

@ -98,8 +98,11 @@ object Parser {
// seqz rd, rs1 => sltiu rd, rs1, 1 // seqz rd, rs1 => sltiu rd, rs1, 1
stringWs("seqz") ~> (reg <~ sep, reg, ok(1)).mapN{ArithImm.sltu}, stringWs("seqz") ~> (reg <~ sep, reg, ok(1)).mapN{ArithImm.sltu},
stringWs("li") ~> (reg ~ sep ~ int).collect{ stringWs("li") ~> (reg ~ sep ~ (hex | int)).collect{
case((a, b), c) if (c.nBitsS <= 12) => ArithImm.add(a, 0, c) case((a, b), c) if (c.nBitsS <= 12) => {
say(s"for c: $c, nBitsS was ${c.nBitsS}")
ArithImm.add(a, 0, c)
}
}, },
@ -122,16 +125,16 @@ object Parser {
//////////////////////////////////////////// ////////////////////////////////////////////
//// load/store //// load/store
stringWs("sw") ~> (reg <~ sep, int <~ char('('), reg <~ char(')')).mapN{case (rs2, offset, rs1) => SW(rs2, rs1, offset)}, stringWs("sw") ~> (reg <~ sep, (hex | int) <~ char('('), reg <~ char(')')).mapN{case (rs2, offset, rs1) => SW(rs2, rs1, offset)},
stringWs("lw") ~> (reg <~ sep, int <~ char('('), reg <~ char(')')).mapN{case (rd, offset, rs1) => LW(rd, rs1, offset)}, stringWs("lw") ~> (reg <~ sep, (hex | int) <~ char('('), reg <~ char(')')).mapN{case (rd, offset, rs1) => LW(rd, rs1, offset)},
//////////////////////////////////////////// ////////////////////////////////////////////
//// others //// others
stringWs("auipc") ~> (reg <~ sep, int).mapN{AUIPC.apply}, stringWs("auipc") ~> (reg <~ sep, (hex | int)).mapN{AUIPC.apply},
stringWs("lui") ~> (reg <~ sep, int).mapN{LUI.apply}, stringWs("lui") ~> (reg <~ sep, (hex | int)).mapN{LUI.apply},
many(whitespace) ~> string("nop") ~> ok(Arith.add(0, 0, 0)), many(whitespace) ~> string("nop") ~> ok(Arith.add(0, 0, 0)),
many(whitespace) ~> string("done") ~> ok(DONE), many(whitespace) ~> string("done") ~> ok(DONE),
@ -140,19 +143,18 @@ object Parser {
).map(_.widen[Op]).reduce(_|_) ).map(_.widen[Op]).reduce(_|_)
// def getShiftsHalfWord(offset: Int): (Int, Int) = (offset % 4) match {
// case 0 => (16, 16)
// case 1 => (
// }
val multipleInstructions: Parser[List[Op]] = List( val multipleInstructions: Parser[List[Op]] = List(
stringWs("li") ~> (reg <~ sep, int.map(_.splitLoHi(12))).mapN{ case(rd, (lo, hi)) => List( // stringWs("li") ~> (reg <~ sep, (hex | int).map(_.splitLoHi(20))).mapN{ case(rd, (hi, lo)) => {
stringWs("li") ~> (reg <~ sep, (hex | int).map(_.splitHiLo(20))).mapN{ case(rd, (hi, lo)) => {
say("hello?")
List(
ArithImm.add(rd, rd, lo),
LUI(rd, hi), LUI(rd, hi),
ArithImm.add(rd, 0, lo) )}}.map(_.widen[Op]),
)}.map(_.widen[Op]),
// NOTE: THESE ARE NOT PSEUDO-OPS IN RISV32I! // NOTE: THESE ARE NOT PSEUDO-OPS IN RISC-V32I!
// NOTE: USES A SPECIAL REGISTER // NOTE: USES A SPECIAL REGISTER
// NOTE: PROBABLY BROKEN, NOT EXHAUSTIVELY TESTED!!!
stringWs("lh") ~> (reg <~ sep, int <~ char('('), reg <~ char(')')).mapN{ stringWs("lh") ~> (reg <~ sep, int <~ char('('), reg <~ char(')')).mapN{
case (rd, offset, rs1) if (offset % 4 == 3) => { case (rd, offset, rs1) if (offset % 4 == 3) => {
val placeHolder = if(rd == Reg("a0").value) Reg("a1").value else Reg("a0").value val placeHolder = if(rd == Reg("a0").value) Reg("a1").value else Reg("a0").value