From ae995a7b55c0bcc1802669ccdf8451ff3a81238f Mon Sep 17 00:00:00 2001
From: peteraa <peteraaser@gmail.com>
Date: Fri, 6 Sep 2019 14:44:01 +0200
Subject: [PATCH] Fix hex | int parse issue. Correctly handle li

---
 src/test/scala/RISCV/DataTypes.scala | 13 +++++------
 src/test/scala/RISCV/Parser.scala    | 32 +++++++++++++++-------------
 2 files changed, 24 insertions(+), 21 deletions(-)

diff --git a/src/test/scala/RISCV/DataTypes.scala b/src/test/scala/RISCV/DataTypes.scala
index 12e91c2..180e854 100644
--- a/src/test/scala/RISCV/DataTypes.scala
+++ b/src/test/scala/RISCV/DataTypes.scala
@@ -158,12 +158,13 @@ object Data {
       rightShifted
     }
 
-    def splitLoHi(loBits: Int): (Int, Int) = {
-      val hiBits = 32 - loBits
-      val sep = 31 - loBits
-      val lo = i.field(31, loBits)
-      val hi = i.field(sep, hiBits)
-      (lo, hi)
+    def splitHiLo(hiBits: Int): (Int, Int) = {
+      val loBits = 32 - hiBits
+      val sep = 31 - hiBits
+      val hi = i.field(31, hiBits)
+      val lo = i.field(sep, loBits)
+      say(s"split lo hi for $i with $hiBits high bits and got low: $lo, high: $hi")
+      (hi, lo)
     }
 
     def log2: Int = math.ceil(math.log(i.toDouble)/math.log(2.0)).toInt
diff --git a/src/test/scala/RISCV/Parser.scala b/src/test/scala/RISCV/Parser.scala
index c00bcd2..50da76d 100644
--- a/src/test/scala/RISCV/Parser.scala
+++ b/src/test/scala/RISCV/Parser.scala
@@ -98,8 +98,11 @@ object Parser {
     // seqz rd, rs1 => sltiu rd, rs1, 1
     stringWs("seqz")  ~> (reg <~ sep, reg, ok(1)).mapN{ArithImm.sltu},
 
-    stringWs("li")    ~> (reg ~ sep ~ int).collect{
-      case((a, b), c) if (c.nBitsS <= 12) => ArithImm.add(a, 0, c)
+    stringWs("li")    ~> (reg ~ sep ~ (hex | int)).collect{
+      case((a, b), c) if (c.nBitsS <= 12) => {
+        say(s"for c: $c, nBitsS was ${c.nBitsS}")
+        ArithImm.add(a, 0, c)
+      }
     },
 
 
@@ -122,16 +125,16 @@ object Parser {
 
     ////////////////////////////////////////////
     //// load/store
-    stringWs("sw") ~> (reg <~ sep, int <~ char('('), reg <~ char(')')).mapN{case (rs2, offset, rs1) => SW(rs2, rs1, offset)},
-    stringWs("lw") ~> (reg <~ sep, int <~ char('('), reg <~ char(')')).mapN{case (rd, offset, rs1) => LW(rd, rs1, offset)},
+    stringWs("sw") ~> (reg <~ sep, (hex | int) <~ char('('), reg <~ char(')')).mapN{case (rs2, offset, rs1) => SW(rs2, rs1, offset)},
+    stringWs("lw") ~> (reg <~ sep, (hex | int) <~ char('('), reg <~ char(')')).mapN{case (rd, offset, rs1) => LW(rd, rs1, offset)},
 
 
 
     
     ////////////////////////////////////////////
     //// others
-    stringWs("auipc") ~> (reg <~ sep, int).mapN{AUIPC.apply},
-    stringWs("lui")   ~> (reg <~ sep, int).mapN{LUI.apply},
+    stringWs("auipc") ~> (reg <~ sep, (hex | int)).mapN{AUIPC.apply},
+    stringWs("lui")   ~> (reg <~ sep, (hex | int)).mapN{LUI.apply},
 
     many(whitespace)  ~> string("nop") ~> ok(Arith.add(0, 0, 0)),
     many(whitespace)  ~> string("done") ~> ok(DONE),
@@ -140,19 +143,18 @@ object Parser {
   ).map(_.widen[Op]).reduce(_|_)
 
 
-  // def getShiftsHalfWord(offset: Int): (Int, Int) = (offset % 4) match {
-  //   case 0 => (16, 16)
-  //   case 1 => (
-  // }
-
   val multipleInstructions: Parser[List[Op]] = List(
-    stringWs("li") ~> (reg <~ sep, int.map(_.splitLoHi(12))).mapN{ case(rd, (lo, hi)) => List(
+    // stringWs("li") ~> (reg <~ sep, (hex | int).map(_.splitLoHi(20))).mapN{ case(rd, (hi, lo)) => {
+    stringWs("li") ~> (reg <~ sep, (hex | int).map(_.splitHiLo(20))).mapN{ case(rd, (hi, lo)) => {
+      say("hello?")
+      List(
+      ArithImm.add(rd, rd, lo),
       LUI(rd, hi),
-      ArithImm.add(rd, 0, lo)
-    )}.map(_.widen[Op]),
+    )}}.map(_.widen[Op]),
 
-    // NOTE: THESE ARE NOT PSEUDO-OPS IN RISV32I!
+    // NOTE: THESE ARE NOT PSEUDO-OPS IN RISC-V32I!
     // NOTE: USES A SPECIAL REGISTER
+    // NOTE: PROBABLY BROKEN, NOT EXHAUSTIVELY TESTED!!!
     stringWs("lh") ~> (reg <~ sep, int <~ char('('), reg <~ char(')')).mapN{
       case (rd, offset, rs1) if (offset % 4 == 3) => {
         val placeHolder = if(rd == Reg("a0").value) Reg("a1").value else Reg("a0").value