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Actually fix forwarding.

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This commit is contained in:
Sebastian Bugge 2024-11-01 03:02:36 +01:00
parent 4c684f1718
commit 97b13a813f
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
5 changed files with 78 additions and 79 deletions
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8
src/main/scala/CPU.scala
View file

@ -117,10 +117,6 @@ class CPU extends MultiIOModule {
IF.io.branchAddress := EXBarrier.ALUResultOut
// Forwarding
IDBarrier.forwardExData := EXBarrier.forwardExData
IDBarrier.forwardEx := EXBarrier.forwardEx
IDBarrier.forwardExAddr := EXBarrier.forwardExAddr
IDBarrier.forwardMemData := MEMBarrier.forwardMemData
IDBarrier.forwardMem := MEMBarrier.forwardMem
IDBarrier.forwardMemAddr := MEMBarrier.forwardMemAddr
@ -129,6 +125,10 @@ class CPU extends MultiIOModule {
IDBarrier.forwardWb := MEMBarrier.forwardWb
IDBarrier.forwardWbAddr := MEMBarrier.forwardWbAddr
IDBarrier.forwardIdData := MEMBarrier.forwardIdData
IDBarrier.forwardId := MEMBarrier.forwardId
IDBarrier.forwardIdAddr := MEMBarrier.forwardIdAddr
// Stall
IF.io.stall := ID.io.stall
}

7
src/main/scala/EXBarrier.scala
View file

@ -24,9 +24,6 @@ class EXBarrier extends MultiIOModule {
val branchOut = Output(Bool())
val jumpIn = Input(Bool())
val jumpOut = Output(Bool())
val forwardEx = Output(Bool())
val forwardExAddr = Output(UInt(5.W))
val forwardExData = Output(UInt(32.W))
})
val ALUResult = RegInit(UInt(32.W), 0.U)
@ -64,8 +61,4 @@ class EXBarrier extends MultiIOModule {
val jump = RegInit(Bool(), false.B)
jump := io.jumpIn
io.jumpOut := jump
io.forwardEx := io.writeEnableIn && !io.memReadIn
io.forwardExAddr := io.writeAddrIn
io.forwardExData := io.ALUResultIn
}

124
src/main/scala/IDBarrier.scala
View file

@ -37,15 +37,15 @@ class IDBarrier extends MultiIOModule {
val memWriteIn = Input(Bool())
val memWriteOut = Output(Bool())
val forwardEx = Input(Bool())
val forwardExAddr = Input(UInt(5.W))
val forwardExData = Input(UInt(32.W))
val forwardMem = Input(Bool())
val forwardMemAddr = Input(UInt(5.W))
val forwardMemData = Input(UInt(32.W))
val forwardWb = Input(Bool())
val forwardWbAddr = Input(UInt(5.W))
val forwardWbData = Input(UInt(32.W))
val forwardId = Input(Bool())
val forwardIdAddr = Input(UInt(5.W))
val forwardIdData = Input(UInt(32.W))
})
val isOp1RValue = RegInit(Bool(), false.B)
@ -53,77 +53,69 @@ class IDBarrier extends MultiIOModule {
val isOp2RValue = RegInit(Bool(), false.B)
isOp2RValue := io.isOp2RValue
val op1 = RegInit(SInt(32.W), 0.S)
op1 := Mux(
io.forwardEx && io.isOp1RValue && io.r1AddressIn === io.forwardExAddr,
io.forwardExData.asSInt(),
Mux(
io.forwardMem && io.isOp1RValue && io.r1AddressIn === io.forwardMemAddr,
io.forwardMemData.asSInt(),
Mux(
io.forwardWb && io.isOp1RValue && io.r1AddressIn === io.forwardWbAddr,
io.forwardWbData.asSInt(),
io.op1in.asSInt(),
),
),
)
io.op1out := op1
val op2 = RegInit(SInt(32.W), 0.S)
op2 := Mux(
io.forwardEx && io.isOp2RValue && io.r2AddressIn === io.forwardExAddr,
io.forwardExData.asSInt(),
Mux(
io.forwardMem && io.isOp2RValue && io.r2AddressIn === io.forwardMemAddr,
io.forwardMemData.asSInt(),
Mux(
io.forwardWb && io.isOp2RValue && io.r2AddressIn === io.forwardWbAddr,
io.forwardWbData.asSInt(),
io.op2in,
),
),
)
io.op2out := op2
val r1Value = RegInit(UInt(32.W), 0.U)
r1Value := Mux(
io.forwardEx && io.r1AddressIn === io.forwardExAddr,
io.forwardExData,
Mux(
io.forwardMem && io.isOp1RValue && io.r1AddressIn === io.forwardMemAddr,
io.forwardMemData,
Mux(
io.forwardWb && io.isOp1RValue && io.r1AddressIn === io.forwardWbAddr,
io.forwardWbData,
io.r1ValueIn,
),
),
)
io.r1ValueOut := r1Value
val r2Address = RegInit(UInt(5.W), 0.U)
r2Address := io.r2AddressIn
io.r2AddressOut := r2Address
val r1Address = RegInit(UInt(5.W), 0.U)
r1Address := io.r1AddressIn
io.r1AddressOut := r1Address
val r2Value = RegInit(UInt(32.W), 0.U)
r2Value := Mux(
io.forwardEx && io.r2AddressIn === io.forwardExAddr,
io.forwardExData,
val op1 = RegInit(SInt(32.W), 0.S)
op1 := io.op1in
io.op1out := Mux(
io.forwardMem && isOp1RValue && r1Address === io.forwardMemAddr,
io.forwardMemData.asSInt(),
Mux(
io.forwardMem && io.r2AddressIn === io.forwardMemAddr,
io.forwardMemData,
io.forwardWb && isOp1RValue && r1Address === io.forwardWbAddr,
io.forwardWbData.asSInt(),
Mux(
io.forwardWb && io.r2AddressIn === io.forwardWbAddr,
io.forwardWbData,
io.r2ValueIn,
),
),
)
io.r2ValueOut := r2Value
io.forwardId && isOp1RValue && r1Address === io.forwardIdAddr,
io.forwardIdData.asSInt(),
op1.asSInt(),
)))
val r2Address = RegInit(UInt(5.W), 0.U)
r2Address := io.r2AddressIn
io.r2AddressOut := r2Address
val op2 = RegInit(SInt(32.W), 0.S)
op2 := io.op2in
io.op2out := Mux(
io.forwardMem && isOp2RValue && r2Address === io.forwardMemAddr,
io.forwardMemData.asSInt(),
Mux(
io.forwardWb && isOp2RValue && r2Address === io.forwardWbAddr,
io.forwardWbData.asSInt(),
Mux(
io.forwardId && isOp2RValue && r2Address === io.forwardIdAddr,
io.forwardIdData.asSInt(),
op2.asSInt(),
)))
val r1Value = RegInit(UInt(32.W), 0.U)
r1Value := io.r1ValueIn
io.r1ValueOut := Mux(
io.forwardMem && r1Address === io.forwardMemAddr,
io.forwardMemData,
Mux(
io.forwardWb && r1Address === io.forwardWbAddr,
io.forwardWbData,
Mux(
io.forwardId && r1Address === io.forwardIdAddr,
io.forwardIdData,
r1Value,
)))
val r2Value = RegInit(UInt(32.W), 0.U)
r2Value := io.r2ValueIn
io.r2ValueOut := Mux(
io.forwardMem && r2Address === io.forwardMemAddr,
io.forwardMemData,
Mux(
io.forwardWb && r2Address === io.forwardWbAddr,
io.forwardWbData,
Mux(
io.forwardId && r2Address === io.forwardIdAddr,
io.forwardIdData,
r2Value,
)))
val returnAddr = RegInit(UInt(32.W), 0.U)
returnAddr := io.returnAddrIn

16
src/main/scala/MEMBarrier.scala
View file

@ -18,6 +18,9 @@ class MEMBarrier extends MultiIOModule {
val forwardWb = Output(Bool())
val forwardWbAddr = Output(UInt(5.W))
val forwardWbData = Output(UInt(32.W))
val forwardId = Output(Bool())
val forwardIdAddr = Output(UInt(5.W))
val forwardIdData = Output(UInt(32.W))
})
val memRead = RegInit(Bool(), false.B)
@ -41,5 +44,16 @@ class MEMBarrier extends MultiIOModule {
io.forwardWb := writeEnable
io.forwardWbAddr := writeAddr
io.forwardWbData := Mux(memRead, io.dataIn, data)
io.forwardWbData := io.dataOut
val forwardId = RegInit(Bool(), false.B)
forwardId := writeEnable
val forwardIdAddr = RegInit(UInt(5.W), 0.U)
forwardIdAddr := io.writeAddrOut
val forwardIdData = RegInit(UInt(32.W), 0.U)
forwardIdData := io.dataOut
io.forwardId := forwardId
io.forwardIdAddr := forwardIdAddr
io.forwardIdData := forwardIdData
}

2
src/test/scala/Manifest.scala
View file

@ -19,7 +19,7 @@ import LogParser._
object Manifest {
val singleTest = "load3.s"
val singleTest = "forward1.s"
val nopPadded = false