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Use copy ALU OPs.

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This commit is contained in:
Sebastian Bugge 2024-10-03 14:40:30 +02:00
parent e09a358320
commit 934593fb6f
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
4 changed files with 42 additions and 42 deletions
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6
src/main/scala/Decoder.scala
View file

@ -53,7 +53,7 @@ class Decoder() extends Module {
OR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.OR ),
XOR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.XOR ),
SLT -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLT ),
SLTU -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLTU),
SLTU -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLTU ),
SRA -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRA ),
SRL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRL ),
SLL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLL ),
@ -64,13 +64,13 @@ class Decoder() extends Module {
ORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.OR ),
XORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.XOR ),
SLTI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLT ),
SLTIU -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLTU),
SLTIU -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLTU ),
SRAI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SRA ),
SRLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SRL ),
SLLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLL ),
// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
LUI -> List(Y, N, N, N, N, branchType.DC, Op1Select.Zero, imm, ImmFormat.UTYPE, ALUOps.ADD ),
LUI -> List(Y, N, N, N, N, branchType.DC, Op1Select.DC, imm, ImmFormat.UTYPE, ALUOps.COPY_B),
AUIPC -> List(Y, N, N, N, N, branchType.DC, Op1Select.PC, imm, ImmFormat.UTYPE, ALUOps.ADD ),
// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp

2
src/main/scala/EX.scala
View file

@ -26,6 +26,8 @@ class Execute extends MultiIOModule {
ALUOps.SRA -> (io.op1 >> io.op2(4, 0)),
ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),
ALUOps.COPY_A -> io.op1,
ALUOps.COPY_B -> io.op2,
)
io.ALUResult := MuxLookup(io.ALUOp, 0.S(32.W), ALUOpsMap)

1
src/main/scala/ID.scala
View file

@ -52,7 +52,6 @@ class InstructionDecode extends MultiIOModule {
val select1Map = Array(
Op1Select.rs1 -> registers.io.readData1.asSInt(),
Op1Select.PC -> io.pc.asSInt(),
Op1Select.Zero -> 0.S
)
io.op1 := MuxLookup(decoder.op1Select, 0.S(32.W), select1Map)

7
src/main/scala/ToplevelSignals.scala
View file

@ -80,10 +80,9 @@ object branchType {
using them altogether.
*/
object Op1Select {
val rs1 = 0.asUInt(2.W)
val PC = 1.asUInt(2.W)
val Zero = 2.asUInt(2.W)
val DC = 3.asUInt(2.W)
val rs1 = 0.asUInt(1.W)
val PC = 1.asUInt(1.W)
val DC = 0.asUInt(1.W)
}
object Op2Select {