From 934593fb6fca726d7d7d1d6a3ca0e7668c1109e0 Mon Sep 17 00:00:00 2001 From: Sebastian Bugge Date: Thu, 3 Oct 2024 14:40:30 +0200 Subject: [PATCH] Use copy ALU OPs. --- src/main/scala/Decoder.scala | 54 ++++++++++++++-------------- src/main/scala/EX.scala | 22 ++++++------ src/main/scala/ID.scala | 1 - src/main/scala/ToplevelSignals.scala | 7 ++-- 4 files changed, 42 insertions(+), 42 deletions(-) diff --git a/src/main/scala/Decoder.scala b/src/main/scala/Decoder.scala index 9cc836b..1f8bfab 100644 --- a/src/main/scala/Decoder.scala +++ b/src/main/scala/Decoder.scala @@ -46,36 +46,36 @@ class Decoder() extends Module { */ val opcodeMap: Array[(BitPat, List[UInt])] = Array( - // signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp - ADD -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD ), - SUB -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB ), - AND -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.AND ), - OR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.OR ), - XOR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.XOR ), - SLT -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLT ), - SLTU -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLTU), - SRA -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRA ), - SRL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRL ), - SLL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLL ), + // signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp + ADD -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD ), + SUB -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB ), + AND -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.AND ), + OR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.OR ), + XOR -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.XOR ), + SLT -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLT ), + SLTU -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLTU ), + SRA -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRA ), + SRL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SRL ), + SLL -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SLL ), - // signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp - ADDI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ), - ANDI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.AND ), - ORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.OR ), - XORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.XOR ), - SLTI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLT ), - SLTIU -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLTU), - SRAI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SRA ), - SRLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SRL ), - SLLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLL ), + // signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp + ADDI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ), + ANDI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.AND ), + ORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.OR ), + XORI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.XOR ), + SLTI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLT ), + SLTIU -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLTU ), + SRAI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SRA ), + SRLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SRL ), + SLLI -> List(Y, N, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.SLL ), - // signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp - LUI -> List(Y, N, N, N, N, branchType.DC, Op1Select.Zero, imm, ImmFormat.UTYPE, ALUOps.ADD ), - AUIPC -> List(Y, N, N, N, N, branchType.DC, Op1Select.PC, imm, ImmFormat.UTYPE, ALUOps.ADD ), + // signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp + LUI -> List(Y, N, N, N, N, branchType.DC, Op1Select.DC, imm, ImmFormat.UTYPE, ALUOps.COPY_B), + AUIPC -> List(Y, N, N, N, N, branchType.DC, Op1Select.PC, imm, ImmFormat.UTYPE, ALUOps.ADD ), - // signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp - LW -> List(Y, Y, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ), - SW -> List(N, N, Y, N, N, branchType.DC, rs1, imm, ImmFormat.STYPE, ALUOps.ADD ), + // signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp + LW -> List(Y, Y, N, N, N, branchType.DC, rs1, imm, ImmFormat.ITYPE, ALUOps.ADD ), + SW -> List(N, N, Y, N, N, branchType.DC, rs1, imm, ImmFormat.STYPE, ALUOps.ADD ), ) diff --git a/src/main/scala/EX.scala b/src/main/scala/EX.scala index e31f44e..42fb903 100644 --- a/src/main/scala/EX.scala +++ b/src/main/scala/EX.scala @@ -16,16 +16,18 @@ class Execute extends MultiIOModule { ) val ALUOpsMap = Array ( - ALUOps.ADD -> (io.op1 + io.op2), - ALUOps.SUB -> (io.op1 - io.op2), - ALUOps.AND -> (io.op1 & io.op2), - ALUOps.OR -> (io.op1 | io.op2), - ALUOps.XOR -> (io.op1 ^ io.op2), - ALUOps.SLT -> Mux(io.op1 < io.op2, 1.S, 0.S), - ALUOps.SLTU -> Mux(io.op1.asUInt() < io.op2.asUInt(), 1.S, 0.S), - ALUOps.SRA -> (io.op1 >> io.op2(4, 0)), - ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(), - ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(), + ALUOps.ADD -> (io.op1 + io.op2), + ALUOps.SUB -> (io.op1 - io.op2), + ALUOps.AND -> (io.op1 & io.op2), + ALUOps.OR -> (io.op1 | io.op2), + ALUOps.XOR -> (io.op1 ^ io.op2), + ALUOps.SLT -> Mux(io.op1 < io.op2, 1.S, 0.S), + ALUOps.SLTU -> Mux(io.op1.asUInt() < io.op2.asUInt(), 1.S, 0.S), + ALUOps.SRA -> (io.op1 >> io.op2(4, 0)), + ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(), + ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(), + ALUOps.COPY_A -> io.op1, + ALUOps.COPY_B -> io.op2, ) io.ALUResult := MuxLookup(io.ALUOp, 0.S(32.W), ALUOpsMap) diff --git a/src/main/scala/ID.scala b/src/main/scala/ID.scala index 66ca58f..a39367f 100644 --- a/src/main/scala/ID.scala +++ b/src/main/scala/ID.scala @@ -52,7 +52,6 @@ class InstructionDecode extends MultiIOModule { val select1Map = Array( Op1Select.rs1 -> registers.io.readData1.asSInt(), Op1Select.PC -> io.pc.asSInt(), - Op1Select.Zero -> 0.S ) io.op1 := MuxLookup(decoder.op1Select, 0.S(32.W), select1Map) diff --git a/src/main/scala/ToplevelSignals.scala b/src/main/scala/ToplevelSignals.scala index fdb9f36..7fe70f5 100644 --- a/src/main/scala/ToplevelSignals.scala +++ b/src/main/scala/ToplevelSignals.scala @@ -80,10 +80,9 @@ object branchType { using them altogether. */ object Op1Select { - val rs1 = 0.asUInt(2.W) - val PC = 1.asUInt(2.W) - val Zero = 2.asUInt(2.W) - val DC = 3.asUInt(2.W) + val rs1 = 0.asUInt(1.W) + val PC = 1.asUInt(1.W) + val DC = 0.asUInt(1.W) } object Op2Select {