Use copy ALU OPs.

src/main/scala/Decoder.scala

@@ -70,7 +70,7 @@ class Decoder() extends Module {
     SLLI   -> List(Y,        N,       N,        N,       N,    branchType.DC, rs1,            imm,       ImmFormat.ITYPE,  ALUOps.SLL   ),
 
     // signal      regWrite, memRead, memWrite, branch,  jump, branchType,    Op1Select,      Op2Select, ImmSelect,        ALUOp
-    LUI    -> List(Y,        N,       N,        N,       N,    branchType.DC, Op1Select.Zero, imm,       ImmFormat.UTYPE,  ALUOps.ADD ),
+    LUI    -> List(Y,        N,       N,        N,       N,    branchType.DC, Op1Select.DC,   imm,       ImmFormat.UTYPE,  ALUOps.COPY_B),
     AUIPC  -> List(Y,        N,       N,        N,       N,    branchType.DC, Op1Select.PC,   imm,       ImmFormat.UTYPE,  ALUOps.ADD   ),
 
     // signal      regWrite, memRead, memWrite, branch,  jump, branchType,    Op1Select,      Op2Select, ImmSelect,        ALUOp

src/main/scala/EX.scala

@@ -26,6 +26,8 @@ class Execute extends MultiIOModule {
     ALUOps.SRA    -> (io.op1 >> io.op2(4, 0)),
     ALUOps.SRL    -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
     ALUOps.SLL    -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),
+    ALUOps.COPY_A -> io.op1,
+    ALUOps.COPY_B -> io.op2,
   )
 
   io.ALUResult := MuxLookup(io.ALUOp, 0.S(32.W), ALUOpsMap)

src/main/scala/ID.scala

@@ -52,7 +52,6 @@ class InstructionDecode extends MultiIOModule {
   val select1Map = Array(
     Op1Select.rs1  -> registers.io.readData1.asSInt(),
     Op1Select.PC   -> io.pc.asSInt(),
-    Op1Select.Zero -> 0.S
   )
   io.op1 := MuxLookup(decoder.op1Select, 0.S(32.W), select1Map)
 

src/main/scala/ToplevelSignals.scala

@@ -80,10 +80,9 @@ object branchType {
   using them altogether.
   */
 object Op1Select {
-  val rs1  = 0.asUInt(2.W)
-  val PC   = 1.asUInt(2.W)
-  val Zero = 2.asUInt(2.W)
-  val DC   = 3.asUInt(2.W)
+  val rs1  = 0.asUInt(1.W)
+  val PC   = 1.asUInt(1.W)
+  val DC   = 0.asUInt(1.W)
 }
 
 object Op2Select {