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Use copy ALU OPs.

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This commit is contained in:
Sebastian Bugge 2024-10-03 14:40:30 +02:00
parent e09a358320
commit 934593fb6f
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
4 changed files with 42 additions and 42 deletions
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22
src/main/scala/EX.scala
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@ -16,16 +16,18 @@ class Execute extends MultiIOModule {
)
val ALUOpsMap = Array (
ALUOps.ADD -> (io.op1 + io.op2),
ALUOps.SUB -> (io.op1 - io.op2),
ALUOps.AND -> (io.op1 & io.op2),
ALUOps.OR -> (io.op1 | io.op2),
ALUOps.XOR -> (io.op1 ^ io.op2),
ALUOps.SLT -> Mux(io.op1 < io.op2, 1.S, 0.S),
ALUOps.SLTU -> Mux(io.op1.asUInt() < io.op2.asUInt(), 1.S, 0.S),
ALUOps.SRA -> (io.op1 >> io.op2(4, 0)),
ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),
ALUOps.ADD -> (io.op1 + io.op2),
ALUOps.SUB -> (io.op1 - io.op2),
ALUOps.AND -> (io.op1 & io.op2),
ALUOps.OR -> (io.op1 | io.op2),
ALUOps.XOR -> (io.op1 ^ io.op2),
ALUOps.SLT -> Mux(io.op1 < io.op2, 1.S, 0.S),
ALUOps.SLTU -> Mux(io.op1.asUInt() < io.op2.asUInt(), 1.S, 0.S),
ALUOps.SRA -> (io.op1 >> io.op2(4, 0)),
ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),
ALUOps.COPY_A -> io.op1,
ALUOps.COPY_B -> io.op2,
)
io.ALUResult := MuxLookup(io.ALUOp, 0.S(32.W), ALUOpsMap)