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Rewrite stall to be more modular.

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This commit is contained in:
Sebastian Bugge 2024-11-01 03:13:00 +01:00
parent 97b13a813f
commit 800e7b6eb0
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
1 changed files with 12 additions and 3 deletions
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15
src/main/scala/ID.scala
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@ -89,10 +89,19 @@ class InstructionDecode extends MultiIOModule {
io.branchType := decoder.branchType io.branchType := decoder.branchType
io.writeAddrOut := decoder.instruction.registerRd io.writeAddrOut := decoder.instruction.registerRd
val stallDelay = RegInit(Bool(), false.B) val stallsRemaining = RegInit(UInt(4.W), 0.U)
val stall = Mux(stallDelay, false.B, decoder.controlSignals.memRead) val stallDelay = stallsRemaining > 0.U
stallsRemaining := Mux(
stallDelay,
stallsRemaining - 1.U,
Mux(
decoder.controlSignals.memRead,
1.U,
0.U
))
val stall = stallsRemaining > 1.U || decoder.controlSignals.memRead && !stallDelay
io.stall := stall io.stall := stall
stallDelay := stall
io.jump := Mux(stallDelay, false.B, decoder.controlSignals.jump) io.jump := Mux(stallDelay, false.B, decoder.controlSignals.jump)
io.returnAddr := io.pc + 4.U io.returnAddr := io.pc + 4.U