From 800e7b6eb0cf2e434bbdcb104c2bb8b0a93d7825 Mon Sep 17 00:00:00 2001
From: Sebastian Bugge <vkbugge@hotmail.com>
Date: Fri, 1 Nov 2024 03:13:00 +0100
Subject: [PATCH] Rewrite stall to be more modular.

---
 src/main/scala/ID.scala | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/ID.scala b/src/main/scala/ID.scala
index 8942aa8..a3adb11 100644
--- a/src/main/scala/ID.scala
+++ b/src/main/scala/ID.scala
@@ -89,10 +89,19 @@ class InstructionDecode extends MultiIOModule {
   io.branchType := decoder.branchType
   io.writeAddrOut := decoder.instruction.registerRd
 
-  val stallDelay = RegInit(Bool(), false.B)
-  val stall = Mux(stallDelay, false.B, decoder.controlSignals.memRead)
+  val stallsRemaining = RegInit(UInt(4.W), 0.U)
+  val stallDelay = stallsRemaining > 0.U
+  stallsRemaining := Mux(
+    stallDelay,
+    stallsRemaining - 1.U,
+    Mux(
+      decoder.controlSignals.memRead,
+      1.U,
+      0.U
+    ))
+
+  val stall = stallsRemaining > 1.U || decoder.controlSignals.memRead && !stallDelay
   io.stall :=  stall
-  stallDelay := stall
 
   io.jump := Mux(stallDelay, false.B, decoder.controlSignals.jump)
   io.returnAddr := io.pc + 4.U