Simplify MEMBarrier.

src/main/scala/CPU.scala

@@ -122,14 +122,14 @@ class CPU extends MultiIOModule {
   MEM.io.writeData := EXBarrier.out.r2Value
 
   MEMBarrier.memRead := EXBarrier.out.memRead
-  MEMBarrier.dataIn := MEM.io.dataOut
-  MEMBarrier.writeEnableIn := EXBarrier.out.writeEnable
-  MEMBarrier.writeAddrIn := EXBarrier.out.writeAddr
+  MEMBarrier.in.data := MEM.io.dataOut
+  MEMBarrier.in.writeEnable := EXBarrier.out.writeEnable
+  MEMBarrier.in.writeAddr := EXBarrier.out.writeAddr
 
   // Write back
-  ID.io.writeData := MEMBarrier.dataOut
-  ID.io.writeEnableIn := MEMBarrier.writeEnableOut
-  ID.io.writeAddrIn := MEMBarrier.writeAddrOut
+  ID.io.writeData := MEMBarrier.out.data
+  ID.io.writeEnableIn := MEMBarrier.out.writeEnable
+  ID.io.writeAddrIn := MEMBarrier.out.writeAddr
 
   // Branching
   IF.io.branch := EXBarrier.out.branch

src/main/scala/MEMBarrier.scala

@@ -2,15 +2,17 @@ package FiveStage
 import chisel3._
 import chisel3.experimental.MultiIOModule
 
+class MEMBarrierIO extends Bundle {
+  val data = UInt(32.W)
+  val writeAddr = UInt(5.W)
+  val writeEnable = Bool()
+}
+
 class MEMBarrier extends MultiIOModule {
   val io = IO(
     new Bundle {
-      val dataIn = Input(UInt(32.W))
-      val dataOut = Output(UInt(32.W))
-      val writeAddrIn = Input(UInt(5.W))
-      val writeAddrOut = Output(UInt(5.W))
-      val writeEnableIn = Input(Bool())
-      val writeEnableOut = Output(Bool())
+      val in = Input(new MEMBarrierIO)
+      val out = Output(new MEMBarrierIO)
       val memRead = Input(Bool())
       val forwardMem = Output(new Forwarding)
       val forwardWb = Output(new Forwarding)
@@ -20,36 +22,25 @@ class MEMBarrier extends MultiIOModule {
   val memRead = RegInit(Bool(), false.B)
   memRead := io.memRead
 
-  val data = RegInit(UInt(32.W), 0.U)
-  data := io.dataIn
-  io.dataOut := Mux(memRead, io.dataIn, data)
+  val delay = Reg(new MEMBarrierIO)
+  val delay2 = Reg(new MEMBarrierIO)
 
-  val writeAddr = RegInit(UInt(5.W), 0.U)
-  writeAddr := io.writeAddrIn
-  io.writeAddrOut := writeAddr
+  delay := io.in
+  io.out := delay
+  io.out.data := Mux(memRead, io.in.data, delay.data)
+  delay2 := io.out
 
-  val writeEnable = RegInit(Bool(), false.B)
-  writeEnable := io.writeEnableIn
-  io.writeEnableOut := writeEnable
+  io.forwardMem.write := io.in.writeEnable && !io.memRead
+  io.forwardMem.writeAddr := io.in.writeAddr
+  io.forwardMem.writeData := io.in.data
 
-  io.forwardMem.write := io.writeEnableIn && !io.memRead
-  io.forwardMem.writeAddr := io.writeAddrIn
-  io.forwardMem.writeData := io.dataIn
+  io.forwardWb.write := io.out.writeEnable
+  io.forwardWb.writeAddr := io.out.writeAddr
+  io.forwardWb.writeData := io.out.data
 
-  io.forwardWb.write := writeEnable
-  io.forwardWb.writeAddr := writeAddr
-  io.forwardWb.writeData := io.dataOut
-
-  val forwardId = RegInit(Bool(), false.B)
-  forwardId := writeEnable
-  val forwardIdAddr = RegInit(UInt(5.W), 0.U)
-  forwardIdAddr := io.writeAddrOut
-  val forwardIdData = RegInit(UInt(32.W), 0.U)
-  forwardIdData := io.dataOut
-
-  io.forwardId.write := forwardId
-  io.forwardId.writeAddr := forwardIdAddr
-  io.forwardId.writeData := forwardIdData
+  io.forwardId.write := delay2.writeEnable
+  io.forwardId.writeAddr := delay2.writeAddr
+  io.forwardId.writeData := delay2.data
 }
 
 class Forwarding extends Bundle {