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Simplify MEMBarrier.

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This commit is contained in:
Sebastian Bugge 2024-11-08 01:47:20 +01:00
parent 9192d576e7
commit 4cfd8268fd
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
2 changed files with 29 additions and 38 deletions
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12
src/main/scala/CPU.scala
View file

@ -122,14 +122,14 @@ class CPU extends MultiIOModule {
MEM.io.writeData := EXBarrier.out.r2Value MEM.io.writeData := EXBarrier.out.r2Value
MEMBarrier.memRead := EXBarrier.out.memRead MEMBarrier.memRead := EXBarrier.out.memRead
MEMBarrier.dataIn := MEM.io.dataOut MEMBarrier.in.data := MEM.io.dataOut
MEMBarrier.writeEnableIn := EXBarrier.out.writeEnable MEMBarrier.in.writeEnable := EXBarrier.out.writeEnable
MEMBarrier.writeAddrIn := EXBarrier.out.writeAddr MEMBarrier.in.writeAddr := EXBarrier.out.writeAddr
// Write back // Write back
ID.io.writeData := MEMBarrier.dataOut ID.io.writeData := MEMBarrier.out.data
ID.io.writeEnableIn := MEMBarrier.writeEnableOut ID.io.writeEnableIn := MEMBarrier.out.writeEnable
ID.io.writeAddrIn := MEMBarrier.writeAddrOut ID.io.writeAddrIn := MEMBarrier.out.writeAddr
// Branching // Branching
IF.io.branch := EXBarrier.out.branch IF.io.branch := EXBarrier.out.branch

55
src/main/scala/MEMBarrier.scala
View file

@ -2,15 +2,17 @@ package FiveStage
import chisel3._ import chisel3._
import chisel3.experimental.MultiIOModule import chisel3.experimental.MultiIOModule
class MEMBarrierIO extends Bundle {
val data = UInt(32.W)
val writeAddr = UInt(5.W)
val writeEnable = Bool()
}
class MEMBarrier extends MultiIOModule { class MEMBarrier extends MultiIOModule {
val io = IO( val io = IO(
new Bundle { new Bundle {
val dataIn = Input(UInt(32.W)) val in = Input(new MEMBarrierIO)
val dataOut = Output(UInt(32.W)) val out = Output(new MEMBarrierIO)
val writeAddrIn = Input(UInt(5.W))
val writeAddrOut = Output(UInt(5.W))
val writeEnableIn = Input(Bool())
val writeEnableOut = Output(Bool())
val memRead = Input(Bool()) val memRead = Input(Bool())
val forwardMem = Output(new Forwarding) val forwardMem = Output(new Forwarding)
val forwardWb = Output(new Forwarding) val forwardWb = Output(new Forwarding)
@ -20,36 +22,25 @@ class MEMBarrier extends MultiIOModule {
val memRead = RegInit(Bool(), false.B) val memRead = RegInit(Bool(), false.B)
memRead := io.memRead memRead := io.memRead
val data = RegInit(UInt(32.W), 0.U) val delay = Reg(new MEMBarrierIO)
data := io.dataIn val delay2 = Reg(new MEMBarrierIO)
io.dataOut := Mux(memRead, io.dataIn, data)
val writeAddr = RegInit(UInt(5.W), 0.U) delay := io.in
writeAddr := io.writeAddrIn io.out := delay
io.writeAddrOut := writeAddr io.out.data := Mux(memRead, io.in.data, delay.data)
delay2 := io.out
val writeEnable = RegInit(Bool(), false.B) io.forwardMem.write := io.in.writeEnable && !io.memRead
writeEnable := io.writeEnableIn io.forwardMem.writeAddr := io.in.writeAddr
io.writeEnableOut := writeEnable io.forwardMem.writeData := io.in.data
io.forwardMem.write := io.writeEnableIn && !io.memRead io.forwardWb.write := io.out.writeEnable
io.forwardMem.writeAddr := io.writeAddrIn io.forwardWb.writeAddr := io.out.writeAddr
io.forwardMem.writeData := io.dataIn io.forwardWb.writeData := io.out.data
io.forwardWb.write := writeEnable io.forwardId.write := delay2.writeEnable
io.forwardWb.writeAddr := writeAddr io.forwardId.writeAddr := delay2.writeAddr
io.forwardWb.writeData := io.dataOut io.forwardId.writeData := delay2.data
val forwardId = RegInit(Bool(), false.B)
forwardId := writeEnable
val forwardIdAddr = RegInit(UInt(5.W), 0.U)
forwardIdAddr := io.writeAddrOut
val forwardIdData = RegInit(UInt(32.W), 0.U)
forwardIdData := io.dataOut
io.forwardId.write := forwardId
io.forwardId.writeAddr := forwardIdAddr
io.forwardId.writeData := forwardIdData
} }
class Forwarding extends Bundle { class Forwarding extends Bundle {