Fix mem-read sync.

src/main/scala/CPU.scala

@@ -114,7 +114,7 @@ class CPU extends MultiIOModule {
 
   // Branching
   IF.io.branch := EXBarrier.branchOut
-  IF.io.branchAddress := EXBarrier.branchAddress
+  IF.io.branchAddress := EXBarrier.ALUResultOut
 
   // Forwarding
   IDBarrier.forwardExData := EXBarrier.forwardExData

src/main/scala/EXBarrier.scala

@@ -8,7 +8,6 @@ class EXBarrier extends MultiIOModule {
     new Bundle {
       val ALUResultIn = Input(UInt(32.W))
       val ALUResultOut = Output(UInt(32.W))
-      val branchAddress = Output(UInt(32.W))
       val returnAddrIn = Input(UInt(32.W))
       val returnAddrOut = Output(UInt(32.W))
       val r2ValueIn = Input(UInt(32.W))
@@ -30,10 +29,9 @@ class EXBarrier extends MultiIOModule {
       val forwardExData = Output(UInt(32.W))
     })
 
-  io.ALUResultOut := io.ALUResultIn
+  val ALUResult = RegInit(UInt(32.W), 0.U)
-  val branchAddress = RegInit(UInt(32.W), 0.U)
+  ALUResult := io.ALUResultIn
-  branchAddress := io.ALUResultIn
+  io.ALUResultOut := ALUResult
-  io.branchAddress := branchAddress
 
   val returnAddr = RegInit(UInt(32.W), 0.U)
   returnAddr := io.returnAddrIn

src/main/scala/MEM.scala

@@ -18,7 +18,7 @@ class MemoryFetch() extends MultiIOModule {
 
   val io = IO(
     new Bundle {
-      val ALUResult = Input(UInt(32.W)) // We get ALUResult one cycle early
+      val ALUResult = Input(UInt(32.W))
       val writeData = Input(UInt(32.W))
       val readMem = Input(Bool())
       val writeMem = Input(Bool())
@@ -40,13 +40,12 @@ class MemoryFetch() extends MultiIOModule {
     * Your code here.
     */
 
-  // ALUResult is one cycle early!
-  val ALUResult = RegInit(UInt(32.W), 0.U)
-  ALUResult := io.ALUResult
-
   DMEM.io.dataIn      := io.writeData
   DMEM.io.writeEnable := io.writeMem
+  DMEM.io.dataAddress := io.ALUResult
 
-  DMEM.io.dataAddress := Mux(io.writeMem, ALUResult, io.ALUResult)
+  val readMem = RegInit(Bool(), false.B)
-  io.dataOut := Mux(io.readMem, DMEM.io.dataOut, Mux(io.jump, io.returnAddr, ALUResult))
+  readMem := io.readMem
+
+  io.dataOut := Mux(readMem, DMEM.io.dataOut, Mux(io.jump, io.returnAddr, io.ALUResult))
 }

src/main/scala/MEMBarrier.scala

@@ -25,7 +25,7 @@ class MEMBarrier extends MultiIOModule {
 
   val data = RegInit(UInt(32.W), 0.U)
   data := io.dataIn
-  io.dataOut := data
+  io.dataOut := Mux(memRead, io.dataIn, data)
 
   val writeAddr = RegInit(UInt(5.W), 0.U)
   writeAddr := io.writeAddrIn
@@ -35,11 +35,11 @@ class MEMBarrier extends MultiIOModule {
   writeEnable := io.writeEnableIn
   io.writeEnableOut := writeEnable
 
-  io.forwardMem := io.writeEnableIn
+  io.forwardMem := io.writeEnableIn && !io.memRead
   io.forwardMemAddr := io.writeAddrIn
   io.forwardMemData := io.dataIn
 
   io.forwardWb := writeEnable
   io.forwardWbAddr := writeAddr
-  io.forwardWbData := data
+  io.forwardWbData := Mux(memRead, io.dataIn, data)
 }

src/test/scala/Manifest.scala

@@ -19,7 +19,7 @@ import LogParser._
 
 object Manifest {
 
-  val singleTest = "forward2.s"
+  val singleTest = "load3.s"
 
   val nopPadded = false