From 4c684f1718df16e7d0a290bad8b0de3ede7dbdae Mon Sep 17 00:00:00 2001 From: Sebastian Bugge Date: Fri, 1 Nov 2024 00:15:41 +0100 Subject: [PATCH] Fix mem-read sync. --- src/main/scala/CPU.scala | 2 +- src/main/scala/EXBarrier.scala | 8 +++----- src/main/scala/MEM.scala | 13 ++++++------- src/main/scala/MEMBarrier.scala | 6 +++--- src/test/scala/Manifest.scala | 2 +- 5 files changed, 14 insertions(+), 17 deletions(-) diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala index 8cf16a9..bc6ffe1 100644 --- a/src/main/scala/CPU.scala +++ b/src/main/scala/CPU.scala @@ -114,7 +114,7 @@ class CPU extends MultiIOModule { // Branching IF.io.branch := EXBarrier.branchOut - IF.io.branchAddress := EXBarrier.branchAddress + IF.io.branchAddress := EXBarrier.ALUResultOut // Forwarding IDBarrier.forwardExData := EXBarrier.forwardExData diff --git a/src/main/scala/EXBarrier.scala b/src/main/scala/EXBarrier.scala index 16f9b1f..9ba6cfc 100644 --- a/src/main/scala/EXBarrier.scala +++ b/src/main/scala/EXBarrier.scala @@ -8,7 +8,6 @@ class EXBarrier extends MultiIOModule { new Bundle { val ALUResultIn = Input(UInt(32.W)) val ALUResultOut = Output(UInt(32.W)) - val branchAddress = Output(UInt(32.W)) val returnAddrIn = Input(UInt(32.W)) val returnAddrOut = Output(UInt(32.W)) val r2ValueIn = Input(UInt(32.W)) @@ -30,10 +29,9 @@ class EXBarrier extends MultiIOModule { val forwardExData = Output(UInt(32.W)) }) - io.ALUResultOut := io.ALUResultIn - val branchAddress = RegInit(UInt(32.W), 0.U) - branchAddress := io.ALUResultIn - io.branchAddress := branchAddress + val ALUResult = RegInit(UInt(32.W), 0.U) + ALUResult := io.ALUResultIn + io.ALUResultOut := ALUResult val returnAddr = RegInit(UInt(32.W), 0.U) returnAddr := io.returnAddrIn diff --git a/src/main/scala/MEM.scala b/src/main/scala/MEM.scala index 669d53f..0cbeb5b 100644 --- a/src/main/scala/MEM.scala +++ b/src/main/scala/MEM.scala @@ -18,7 +18,7 @@ class MemoryFetch() extends MultiIOModule { val io = IO( new Bundle { - val ALUResult = Input(UInt(32.W)) // We get ALUResult one cycle early + val ALUResult = Input(UInt(32.W)) val writeData = Input(UInt(32.W)) val readMem = Input(Bool()) val writeMem = Input(Bool()) @@ -40,13 +40,12 @@ class MemoryFetch() extends MultiIOModule { * Your code here. */ - // ALUResult is one cycle early! - val ALUResult = RegInit(UInt(32.W), 0.U) - ALUResult := io.ALUResult - DMEM.io.dataIn := io.writeData DMEM.io.writeEnable := io.writeMem + DMEM.io.dataAddress := io.ALUResult - DMEM.io.dataAddress := Mux(io.writeMem, ALUResult, io.ALUResult) - io.dataOut := Mux(io.readMem, DMEM.io.dataOut, Mux(io.jump, io.returnAddr, ALUResult)) + val readMem = RegInit(Bool(), false.B) + readMem := io.readMem + + io.dataOut := Mux(readMem, DMEM.io.dataOut, Mux(io.jump, io.returnAddr, io.ALUResult)) } diff --git a/src/main/scala/MEMBarrier.scala b/src/main/scala/MEMBarrier.scala index 27b636c..ed36d1a 100644 --- a/src/main/scala/MEMBarrier.scala +++ b/src/main/scala/MEMBarrier.scala @@ -25,7 +25,7 @@ class MEMBarrier extends MultiIOModule { val data = RegInit(UInt(32.W), 0.U) data := io.dataIn - io.dataOut := data + io.dataOut := Mux(memRead, io.dataIn, data) val writeAddr = RegInit(UInt(5.W), 0.U) writeAddr := io.writeAddrIn @@ -35,11 +35,11 @@ class MEMBarrier extends MultiIOModule { writeEnable := io.writeEnableIn io.writeEnableOut := writeEnable - io.forwardMem := io.writeEnableIn + io.forwardMem := io.writeEnableIn && !io.memRead io.forwardMemAddr := io.writeAddrIn io.forwardMemData := io.dataIn io.forwardWb := writeEnable io.forwardWbAddr := writeAddr - io.forwardWbData := data + io.forwardWbData := Mux(memRead, io.dataIn, data) } diff --git a/src/test/scala/Manifest.scala b/src/test/scala/Manifest.scala index 0f2241a..eaf8823 100644 --- a/src/test/scala/Manifest.scala +++ b/src/test/scala/Manifest.scala @@ -19,7 +19,7 @@ import LogParser._ object Manifest { - val singleTest = "forward2.s" + val singleTest = "load3.s" val nopPadded = false