kaholaz/TDT4255
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Fix mem-read sync.

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This commit is contained in:
Sebastian Bugge 2024-11-01 00:15:41 +01:00
parent af2cc43540
commit 4c684f1718
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
5 changed files with 14 additions and 17 deletions
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13
src/main/scala/MEM.scala
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@ -18,7 +18,7 @@ class MemoryFetch() extends MultiIOModule {
val io = IO(
new Bundle {
val ALUResult = Input(UInt(32.W)) // We get ALUResult one cycle early
val ALUResult = Input(UInt(32.W))
val writeData = Input(UInt(32.W))
val readMem = Input(Bool())
val writeMem = Input(Bool())
@ -40,13 +40,12 @@ class MemoryFetch() extends MultiIOModule {
* Your code here.
*/
// ALUResult is one cycle early!
val ALUResult = RegInit(UInt(32.W), 0.U)
ALUResult := io.ALUResult
DMEM.io.dataIn := io.writeData
DMEM.io.writeEnable := io.writeMem
DMEM.io.dataAddress := io.ALUResult
DMEM.io.dataAddress := Mux(io.writeMem, ALUResult, io.ALUResult)
io.dataOut := Mux(io.readMem, DMEM.io.dataOut, Mux(io.jump, io.returnAddr, ALUResult))
val readMem = RegInit(Bool(), false.B)
readMem := io.readMem
io.dataOut := Mux(readMem, DMEM.io.dataOut, Mux(io.jump, io.returnAddr, io.ALUResult))
}