Fix mem-read sync.
This commit is contained in:
parent
af2cc43540
commit
4c684f1718
5 changed files with 14 additions and 17 deletions
|
@ -8,7 +8,6 @@ class EXBarrier extends MultiIOModule {
|
|||
new Bundle {
|
||||
val ALUResultIn = Input(UInt(32.W))
|
||||
val ALUResultOut = Output(UInt(32.W))
|
||||
val branchAddress = Output(UInt(32.W))
|
||||
val returnAddrIn = Input(UInt(32.W))
|
||||
val returnAddrOut = Output(UInt(32.W))
|
||||
val r2ValueIn = Input(UInt(32.W))
|
||||
|
@ -30,10 +29,9 @@ class EXBarrier extends MultiIOModule {
|
|||
val forwardExData = Output(UInt(32.W))
|
||||
})
|
||||
|
||||
io.ALUResultOut := io.ALUResultIn
|
||||
val branchAddress = RegInit(UInt(32.W), 0.U)
|
||||
branchAddress := io.ALUResultIn
|
||||
io.branchAddress := branchAddress
|
||||
val ALUResult = RegInit(UInt(32.W), 0.U)
|
||||
ALUResult := io.ALUResultIn
|
||||
io.ALUResultOut := ALUResult
|
||||
|
||||
val returnAddr = RegInit(UInt(32.W), 0.U)
|
||||
returnAddr := io.returnAddrIn
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue