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Simplify EXBarrier.

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This commit is contained in:
Sebastian Bugge 2024-11-08 01:06:07 +01:00
parent 6d6474530c
commit 42d77a0d85
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
2 changed files with 37 additions and 78 deletions
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45
src/main/scala/CPU.scala
View file

@ -104,27 +104,27 @@ class CPU extends MultiIOModule {
EX.io.rs1ValueIn := forward(IDBarrier.r1ValueOut, IDBarrier.r1AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt() EX.io.rs1ValueIn := forward(IDBarrier.r1ValueOut, IDBarrier.r1AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
EX.io.rs2ValueIn := forward(IDBarrier.r2ValueOut, IDBarrier.r2AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt() EX.io.rs2ValueIn := forward(IDBarrier.r2ValueOut, IDBarrier.r2AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
EXBarrier.r2ValueIn := EX.io.rs2ValueOut.asUInt() EXBarrier.in.r2Value := EX.io.rs2ValueOut.asUInt()
EXBarrier.ALUResultIn := EX.io.ALUResult.asUInt() EXBarrier.in.ALUResult := EX.io.ALUResult.asUInt()
EXBarrier.branchIn := EX.io.branch EXBarrier.in.branch := EX.io.branch
EXBarrier.jumpIn := IDBarrier.jumpOut EXBarrier.in.jump := IDBarrier.jumpOut
EXBarrier.returnAddrIn := IDBarrier.returnAddrOut EXBarrier.in.returnAddr := IDBarrier.returnAddrOut
EXBarrier.writeEnableIn := IDBarrier.writeEnableOut EXBarrier.in.writeEnable := IDBarrier.writeEnableOut
EXBarrier.writeAddrIn := IDBarrier.writeAddrOut EXBarrier.in.writeAddr := IDBarrier.writeAddrOut
EXBarrier.memWriteIn := IDBarrier.memWriteOut EXBarrier.in.memWrite := IDBarrier.memWriteOut
EXBarrier.memReadIn := IDBarrier.memReadOut EXBarrier.in.memRead := IDBarrier.memReadOut
MEM.io.ALUResult := EXBarrier.ALUResultOut MEM.io.ALUResult := EXBarrier.out.ALUResult
MEM.io.jump := EXBarrier.jumpOut MEM.io.jump := EXBarrier.out.jump
MEM.io.returnAddr := EXBarrier.returnAddrOut MEM.io.returnAddr := EXBarrier.out.returnAddr
MEM.io.writeMem := EXBarrier.memWriteOut MEM.io.writeMem := EXBarrier.out.memWrite
MEM.io.readMem := EXBarrier.memReadOut MEM.io.readMem := EXBarrier.out.memRead
MEM.io.writeData := EXBarrier.r2ValueOut MEM.io.writeData := EXBarrier.out.r2Value
MEMBarrier.memRead := EXBarrier.memReadOut MEMBarrier.memRead := EXBarrier.out.memRead
MEMBarrier.dataIn := MEM.io.dataOut MEMBarrier.dataIn := MEM.io.dataOut
MEMBarrier.writeEnableIn := EXBarrier.writeEnableOut MEMBarrier.writeEnableIn := EXBarrier.out.writeEnable
MEMBarrier.writeAddrIn := EXBarrier.writeAddrOut MEMBarrier.writeAddrIn := EXBarrier.out.writeAddr
// Write back // Write back
ID.io.writeData := MEMBarrier.dataOut ID.io.writeData := MEMBarrier.dataOut
@ -132,13 +132,8 @@ class CPU extends MultiIOModule {
ID.io.writeAddrIn := MEMBarrier.writeAddrOut ID.io.writeAddrIn := MEMBarrier.writeAddrOut
// Branching // Branching
IF.io.branch := EXBarrier.branchOut IF.io.branch := EXBarrier.out.branch
IF.io.branchAddress := EXBarrier.ALUResultOut IF.io.branchAddress := EXBarrier.out.ALUResult
// Forwarding
IDBarrier.forwardMem := MEMBarrier.forwardMem
IDBarrier.forwardWb := MEMBarrier.forwardWb
IDBarrier.forwardId := MEMBarrier.forwardId
// Stall // Stall
IF.io.stall := ID.io.stall IF.io.stall := ID.io.stall

70
src/main/scala/EXBarrier.scala
View file

@ -3,62 +3,26 @@ package FiveStage
import chisel3._ import chisel3._
import chisel3.experimental.MultiIOModule import chisel3.experimental.MultiIOModule
class EXBarrierIO extends Bundle {
val ALUResult = UInt(32.W)
val returnAddr = UInt(32.W)
val r2Value = UInt(32.W)
val writeAddr = UInt(5.W)
val writeEnable = Bool()
val memRead = Bool()
val memWrite = Bool()
val branch = Bool()
val jump = Bool()
}
class EXBarrier extends MultiIOModule { class EXBarrier extends MultiIOModule {
val io = IO( val io = IO(
new Bundle { new Bundle {
val ALUResultIn = Input(UInt(32.W)) val in = Input(new EXBarrierIO)
val ALUResultOut = Output(UInt(32.W)) val out = Output(new EXBarrierIO)
val returnAddrIn = Input(UInt(32.W))
val returnAddrOut = Output(UInt(32.W))
val r2ValueIn = Input(UInt(32.W))
val r2ValueOut = Output(UInt(32.W))
val writeAddrIn = Input(UInt(5.W))
val writeAddrOut = Output(UInt(5.W))
val writeEnableIn = Input(Bool())
val writeEnableOut = Output(Bool())
val memReadIn = Input(Bool())
val memReadOut = Output(Bool())
val memWriteIn = Input(Bool())
val memWriteOut = Output(Bool())
val branchIn = Input(Bool())
val branchOut = Output(Bool())
val jumpIn = Input(Bool())
val jumpOut = Output(Bool())
}) })
val ALUResult = RegInit(UInt(32.W), 0.U) val delay = Reg(new EXBarrierIO)
ALUResult := io.ALUResultIn delay := io.in
io.ALUResultOut := ALUResult io.out := delay
val returnAddr = RegInit(UInt(32.W), 0.U)
returnAddr := io.returnAddrIn
io.returnAddrOut := returnAddr
val r2Value = RegInit(UInt(32.W), 0.U)
r2Value := io.r2ValueIn
io.r2ValueOut := r2Value
val writeAddr = RegInit(UInt(5.W), 0.U)
writeAddr := io.writeAddrIn
io.writeAddrOut := writeAddr
val writeEnable = RegInit(Bool(), false.B)
writeEnable := io.writeEnableIn
io.writeEnableOut := writeEnable
val memRead = RegInit(Bool(), false.B)
memRead := io.memReadIn
io.memReadOut := memRead
val memWrite = RegInit(Bool(), false.B)
memWrite := io.memWriteIn
io.memWriteOut := memWrite
val branch = RegInit(Bool(), false.B)
branch := io.branchIn
io.branchOut := branch
val jump = RegInit(Bool(), false.B)
jump := io.jumpIn
io.jumpOut := jump
} }