diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala
index 52738b2..8804a34 100644
--- a/src/main/scala/CPU.scala
+++ b/src/main/scala/CPU.scala
@@ -104,27 +104,27 @@ class CPU extends MultiIOModule {
   EX.io.rs1ValueIn := forward(IDBarrier.r1ValueOut, IDBarrier.r1AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
   EX.io.rs2ValueIn := forward(IDBarrier.r2ValueOut, IDBarrier.r2AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
 
-  EXBarrier.r2ValueIn := EX.io.rs2ValueOut.asUInt()
-  EXBarrier.ALUResultIn := EX.io.ALUResult.asUInt()
-  EXBarrier.branchIn := EX.io.branch
-  EXBarrier.jumpIn := IDBarrier.jumpOut
-  EXBarrier.returnAddrIn := IDBarrier.returnAddrOut
-  EXBarrier.writeEnableIn := IDBarrier.writeEnableOut
-  EXBarrier.writeAddrIn := IDBarrier.writeAddrOut
-  EXBarrier.memWriteIn := IDBarrier.memWriteOut
-  EXBarrier.memReadIn := IDBarrier.memReadOut
+  EXBarrier.in.r2Value := EX.io.rs2ValueOut.asUInt()
+  EXBarrier.in.ALUResult := EX.io.ALUResult.asUInt()
+  EXBarrier.in.branch := EX.io.branch
+  EXBarrier.in.jump := IDBarrier.jumpOut
+  EXBarrier.in.returnAddr := IDBarrier.returnAddrOut
+  EXBarrier.in.writeEnable := IDBarrier.writeEnableOut
+  EXBarrier.in.writeAddr := IDBarrier.writeAddrOut
+  EXBarrier.in.memWrite := IDBarrier.memWriteOut
+  EXBarrier.in.memRead := IDBarrier.memReadOut
 
-  MEM.io.ALUResult := EXBarrier.ALUResultOut
-  MEM.io.jump := EXBarrier.jumpOut
-  MEM.io.returnAddr := EXBarrier.returnAddrOut
-  MEM.io.writeMem := EXBarrier.memWriteOut
-  MEM.io.readMem := EXBarrier.memReadOut
-  MEM.io.writeData := EXBarrier.r2ValueOut
+  MEM.io.ALUResult := EXBarrier.out.ALUResult
+  MEM.io.jump := EXBarrier.out.jump
+  MEM.io.returnAddr := EXBarrier.out.returnAddr
+  MEM.io.writeMem := EXBarrier.out.memWrite
+  MEM.io.readMem := EXBarrier.out.memRead
+  MEM.io.writeData := EXBarrier.out.r2Value
 
-  MEMBarrier.memRead := EXBarrier.memReadOut
+  MEMBarrier.memRead := EXBarrier.out.memRead
   MEMBarrier.dataIn := MEM.io.dataOut
-  MEMBarrier.writeEnableIn := EXBarrier.writeEnableOut
-  MEMBarrier.writeAddrIn := EXBarrier.writeAddrOut
+  MEMBarrier.writeEnableIn := EXBarrier.out.writeEnable
+  MEMBarrier.writeAddrIn := EXBarrier.out.writeAddr
 
   // Write back
   ID.io.writeData := MEMBarrier.dataOut
@@ -132,13 +132,8 @@ class CPU extends MultiIOModule {
   ID.io.writeAddrIn := MEMBarrier.writeAddrOut
 
   // Branching
-  IF.io.branch := EXBarrier.branchOut
-  IF.io.branchAddress := EXBarrier.ALUResultOut
-
-  // Forwarding
-  IDBarrier.forwardMem := MEMBarrier.forwardMem
-  IDBarrier.forwardWb := MEMBarrier.forwardWb
-  IDBarrier.forwardId := MEMBarrier.forwardId
+  IF.io.branch := EXBarrier.out.branch
+  IF.io.branchAddress := EXBarrier.out.ALUResult
 
   // Stall
   IF.io.stall := ID.io.stall
diff --git a/src/main/scala/EXBarrier.scala b/src/main/scala/EXBarrier.scala
index 4d74cda..2c79a95 100644
--- a/src/main/scala/EXBarrier.scala
+++ b/src/main/scala/EXBarrier.scala
@@ -3,62 +3,26 @@ package FiveStage
 import chisel3._
 import chisel3.experimental.MultiIOModule
 
+class EXBarrierIO extends Bundle {
+  val ALUResult = UInt(32.W)
+  val returnAddr = UInt(32.W)
+  val r2Value = UInt(32.W)
+  val writeAddr = UInt(5.W)
+  val writeEnable = Bool()
+  val memRead = Bool()
+  val memWrite = Bool()
+  val branch = Bool()
+  val jump = Bool()
+}
+
 class EXBarrier extends MultiIOModule {
   val io = IO(
     new Bundle {
-      val ALUResultIn = Input(UInt(32.W))
-      val ALUResultOut = Output(UInt(32.W))
-      val returnAddrIn = Input(UInt(32.W))
-      val returnAddrOut = Output(UInt(32.W))
-      val r2ValueIn = Input(UInt(32.W))
-      val r2ValueOut = Output(UInt(32.W))
-      val writeAddrIn = Input(UInt(5.W))
-      val writeAddrOut = Output(UInt(5.W))
-      val writeEnableIn = Input(Bool())
-      val writeEnableOut = Output(Bool())
-      val memReadIn = Input(Bool())
-      val memReadOut = Output(Bool())
-      val memWriteIn = Input(Bool())
-      val memWriteOut = Output(Bool())
-      val branchIn = Input(Bool())
-      val branchOut = Output(Bool())
-      val jumpIn = Input(Bool())
-      val jumpOut = Output(Bool())
+      val in = Input(new EXBarrierIO)
+      val out = Output(new EXBarrierIO)
     })
 
-  val ALUResult = RegInit(UInt(32.W), 0.U)
-  ALUResult := io.ALUResultIn
-  io.ALUResultOut := ALUResult
-
-  val returnAddr = RegInit(UInt(32.W), 0.U)
-  returnAddr := io.returnAddrIn
-  io.returnAddrOut := returnAddr
-
-  val r2Value = RegInit(UInt(32.W), 0.U)
-  r2Value := io.r2ValueIn
-  io.r2ValueOut := r2Value
-
-  val writeAddr = RegInit(UInt(5.W), 0.U)
-  writeAddr := io.writeAddrIn
-  io.writeAddrOut := writeAddr
-
-  val writeEnable = RegInit(Bool(), false.B)
-  writeEnable := io.writeEnableIn
-  io.writeEnableOut := writeEnable
-
-  val memRead = RegInit(Bool(), false.B)
-  memRead := io.memReadIn
-  io.memReadOut := memRead
-
-  val memWrite = RegInit(Bool(), false.B)
-  memWrite := io.memWriteIn
-  io.memWriteOut := memWrite
-
-  val branch = RegInit(Bool(), false.B)
-  branch := io.branchIn
-  io.branchOut := branch
-
-  val jump = RegInit(Bool(), false.B)
-  jump := io.jumpIn
-  io.jumpOut := jump
+  val delay = Reg(new EXBarrierIO)
+  delay := io.in
+  io.out := delay
 }