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Simplify EXBarrier.

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This commit is contained in:
Sebastian Bugge 2024-11-08 01:06:07 +01:00
parent 6d6474530c
commit 42d77a0d85
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
2 changed files with 37 additions and 78 deletions
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45
src/main/scala/CPU.scala
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@ -104,27 +104,27 @@ class CPU extends MultiIOModule {
EX.io.rs1ValueIn := forward(IDBarrier.r1ValueOut, IDBarrier.r1AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
EX.io.rs2ValueIn := forward(IDBarrier.r2ValueOut, IDBarrier.r2AddressOut, true.B, mem = MEMBarrier.forwardMem, wb = MEMBarrier.forwardWb, id = MEMBarrier.forwardId).asSInt()
EXBarrier.r2ValueIn := EX.io.rs2ValueOut.asUInt()
EXBarrier.ALUResultIn := EX.io.ALUResult.asUInt()
EXBarrier.branchIn := EX.io.branch
EXBarrier.jumpIn := IDBarrier.jumpOut
EXBarrier.returnAddrIn := IDBarrier.returnAddrOut
EXBarrier.writeEnableIn := IDBarrier.writeEnableOut
EXBarrier.writeAddrIn := IDBarrier.writeAddrOut
EXBarrier.memWriteIn := IDBarrier.memWriteOut
EXBarrier.memReadIn := IDBarrier.memReadOut
EXBarrier.in.r2Value := EX.io.rs2ValueOut.asUInt()
EXBarrier.in.ALUResult := EX.io.ALUResult.asUInt()
EXBarrier.in.branch := EX.io.branch
EXBarrier.in.jump := IDBarrier.jumpOut
EXBarrier.in.returnAddr := IDBarrier.returnAddrOut
EXBarrier.in.writeEnable := IDBarrier.writeEnableOut
EXBarrier.in.writeAddr := IDBarrier.writeAddrOut
EXBarrier.in.memWrite := IDBarrier.memWriteOut
EXBarrier.in.memRead := IDBarrier.memReadOut
MEM.io.ALUResult := EXBarrier.ALUResultOut
MEM.io.jump := EXBarrier.jumpOut
MEM.io.returnAddr := EXBarrier.returnAddrOut
MEM.io.writeMem := EXBarrier.memWriteOut
MEM.io.readMem := EXBarrier.memReadOut
MEM.io.writeData := EXBarrier.r2ValueOut
MEM.io.ALUResult := EXBarrier.out.ALUResult
MEM.io.jump := EXBarrier.out.jump
MEM.io.returnAddr := EXBarrier.out.returnAddr
MEM.io.writeMem := EXBarrier.out.memWrite
MEM.io.readMem := EXBarrier.out.memRead
MEM.io.writeData := EXBarrier.out.r2Value
MEMBarrier.memRead := EXBarrier.memReadOut
MEMBarrier.memRead := EXBarrier.out.memRead
MEMBarrier.dataIn := MEM.io.dataOut
MEMBarrier.writeEnableIn := EXBarrier.writeEnableOut
MEMBarrier.writeAddrIn := EXBarrier.writeAddrOut
MEMBarrier.writeEnableIn := EXBarrier.out.writeEnable
MEMBarrier.writeAddrIn := EXBarrier.out.writeAddr
// Write back
ID.io.writeData := MEMBarrier.dataOut
@ -132,13 +132,8 @@ class CPU extends MultiIOModule {
ID.io.writeAddrIn := MEMBarrier.writeAddrOut
// Branching
IF.io.branch := EXBarrier.branchOut
IF.io.branchAddress := EXBarrier.ALUResultOut
// Forwarding
IDBarrier.forwardMem := MEMBarrier.forwardMem
IDBarrier.forwardWb := MEMBarrier.forwardWb
IDBarrier.forwardId := MEMBarrier.forwardId
IF.io.branch := EXBarrier.out.branch
IF.io.branchAddress := EXBarrier.out.ALUResult
// Stall
IF.io.stall := ID.io.stall