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Working store and load.

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This commit is contained in:
Sebastian Bugge 2024-09-27 08:14:15 +02:00
parent f7c93b1292
commit 39a6c5f87e
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
1 changed files with 8 additions and 3 deletions
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11
src/main/scala/MEM.scala
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@ -40,14 +40,19 @@ class MemoryFetch() extends MultiIOModule {
/** /**
* Your code here. * Your code here.
*/ */
DMEM.io.dataIn := io.writeData
DMEM.io.dataAddress := io.ALUResult
DMEM.io.writeEnable := io.writeMem
// ALUResult is one cycle early! // ALUResult is one cycle early!
val ALUResult = RegInit(UInt(32.W), 0.U) val ALUResult = RegInit(UInt(32.W), 0.U)
ALUResult := io.ALUResult ALUResult := io.ALUResult
DMEM.io.dataIn := io.writeData
DMEM.io.writeEnable := io.writeMem
when(io.writeMem) {
DMEM.io.dataAddress := ALUResult
}.otherwise(DMEM.io.dataAddress := io.ALUResult)
when(io.readMem) { when(io.readMem) {
io.dataOut := DMEM.io.dataOut io.dataOut := DMEM.io.dataOut
}.otherwise(io.dataOut := ALUResult) }.otherwise(io.dataOut := ALUResult)