From 39a6c5f87e4b17d64255bd81bc18ba2bda2afe21 Mon Sep 17 00:00:00 2001
From: Sebastian Bugge <vkbugge@hotmail.com>
Date: Fri, 27 Sep 2024 08:14:15 +0200
Subject: [PATCH] Working store and load.

---
 src/main/scala/MEM.scala | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/MEM.scala b/src/main/scala/MEM.scala
index 31f94d2..a136fa4 100644
--- a/src/main/scala/MEM.scala
+++ b/src/main/scala/MEM.scala
@@ -40,14 +40,19 @@ class MemoryFetch() extends MultiIOModule {
   /**
     * Your code here.
     */
-  DMEM.io.dataIn      := io.writeData
-  DMEM.io.dataAddress := io.ALUResult
-  DMEM.io.writeEnable := io.writeMem
 
   // ALUResult is one cycle early!
   val ALUResult = RegInit(UInt(32.W), 0.U)
   ALUResult := io.ALUResult
 
+  DMEM.io.dataIn      := io.writeData
+  DMEM.io.writeEnable := io.writeMem
+
+  when(io.writeMem) {
+    DMEM.io.dataAddress := ALUResult
+  }.otherwise(DMEM.io.dataAddress := io.ALUResult)
+
+
   when(io.readMem) {
     io.dataOut := DMEM.io.dataOut
   }.otherwise(io.dataOut := ALUResult)