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Merge branch 'master' of https://github.com/PeterAaser/TDT4255_EX2

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peteraa 2020-06-29 16:19:56 +02:00
commit 2e37f0b8d7
17 changed files with 478 additions and 260 deletions
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41
src/main/scala/Decoder.scala
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@ -8,7 +8,7 @@ import chisel3.util.ListLookup
* This module is mostly done, but you will have to fill in the blanks in opcodeMap.
* You may want to add more signals to be decoded in this module depending on your
* design if you so desire.
*
*
* In the "classic" 5 stage decoder signals such as op1select and immType
* are not included, however I have added them to my design, and similarily you might
* find it useful to add more
@ -36,23 +36,23 @@ class Decoder() extends Module {
val Y = 1.asUInt(1.W)
/**
* In scala we sometimes (ab)use the `->` operator to create tuples.
* In scala we sometimes (ab)use the `->` operator to create tuples.
* The reason for this is that it serves as convenient sugar to make maps.
*
*
* This doesn't matter to you, just fill in the blanks in the style currently
* used, I just want to demystify some of the scala magic.
*
*
* `a -> b` == `(a, b)` == `Tuple2(a, b)`
*/
val opcodeMap: Array[(BitPat, List[UInt])] = Array(
// signal memToReg, regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
LW -> List(Y, Y, Y, N, N, N, branchType.DC, rs1, imm, ITYPE, ALUOps.ADD),
// signal regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
LW -> List(Y, Y, N, N, N, branchType.DC, rs1, imm, ITYPE, ALUOps.ADD),
SW -> List(N, N, N, Y, N, N, branchType.DC, rs1, imm, STYPE, ALUOps.ADD),
SW -> List(N, N, Y, N, N, branchType.DC, rs1, imm, STYPE, ALUOps.ADD),
ADD -> List(N, Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD),
SUB -> List(N, Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB),
ADD -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD),
SUB -> List(Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB),
/**
TODO: Fill in the blanks
@ -60,23 +60,22 @@ class Decoder() extends Module {
)
val NOP = List(N, N, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.DC)
val NOP = List(N, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.DC)
val decodedControlSignals = ListLookup(
io.instruction.asUInt(),
NOP,
opcodeMap)
io.controlSignals.memToReg := decodedControlSignals(0)
io.controlSignals.regWrite := decodedControlSignals(1)
io.controlSignals.memRead := decodedControlSignals(2)
io.controlSignals.memWrite := decodedControlSignals(3)
io.controlSignals.branch := decodedControlSignals(4)
io.controlSignals.jump := decodedControlSignals(5)
io.controlSignals.regWrite := decodedControlSignals(0)
io.controlSignals.memRead := decodedControlSignals(1)
io.controlSignals.memWrite := decodedControlSignals(2)
io.controlSignals.branch := decodedControlSignals(3)
io.controlSignals.jump := decodedControlSignals(4)
io.branchType := decodedControlSignals(6)
io.op1Select := decodedControlSignals(7)
io.op2Select := decodedControlSignals(8)
io.immType := decodedControlSignals(9)
io.ALUop := decodedControlSignals(10)
io.branchType := decodedControlSignals(5)
io.op1Select := decodedControlSignals(6)
io.op2Select := decodedControlSignals(7)
io.immType := decodedControlSignals(8)
io.ALUop := decodedControlSignals(9)
}

2
src/main/scala/ToplevelSignals.scala
View file

@ -39,7 +39,6 @@ object Instruction {
class ControlSignals extends Bundle(){
val memToReg = Bool()
val regWrite = Bool()
val memRead = Bool()
val memWrite = Bool()
@ -51,7 +50,6 @@ class ControlSignals extends Bundle(){
object ControlSignals {
def nop: ControlSignals = {
val b = Wire(new ControlSignals)
b.memToReg := false.B
b.regWrite := false.B
b.memRead := false.B
b.memWrite := false.B