Simplify forwarding.
This commit is contained in:
parent
804e1ed2e6
commit
1eefeca2d6
7 changed files with 70 additions and 61 deletions
|
@ -117,17 +117,9 @@ class CPU extends MultiIOModule {
|
||||||
IF.io.branchAddress := EXBarrier.ALUResultOut
|
IF.io.branchAddress := EXBarrier.ALUResultOut
|
||||||
|
|
||||||
// Forwarding
|
// Forwarding
|
||||||
IDBarrier.forwardMemData := MEMBarrier.forwardMemData
|
|
||||||
IDBarrier.forwardMem := MEMBarrier.forwardMem
|
IDBarrier.forwardMem := MEMBarrier.forwardMem
|
||||||
IDBarrier.forwardMemAddr := MEMBarrier.forwardMemAddr
|
|
||||||
|
|
||||||
IDBarrier.forwardWbData := MEMBarrier.forwardWbData
|
|
||||||
IDBarrier.forwardWb := MEMBarrier.forwardWb
|
IDBarrier.forwardWb := MEMBarrier.forwardWb
|
||||||
IDBarrier.forwardWbAddr := MEMBarrier.forwardWbAddr
|
|
||||||
|
|
||||||
IDBarrier.forwardIdData := MEMBarrier.forwardIdData
|
|
||||||
IDBarrier.forwardId := MEMBarrier.forwardId
|
IDBarrier.forwardId := MEMBarrier.forwardId
|
||||||
IDBarrier.forwardIdAddr := MEMBarrier.forwardIdAddr
|
|
||||||
|
|
||||||
// Stall
|
// Stall
|
||||||
IF.io.stall := ID.io.stall
|
IF.io.stall := ID.io.stall
|
||||||
|
|
|
@ -37,15 +37,9 @@ class IDBarrier extends MultiIOModule {
|
||||||
val memWriteIn = Input(Bool())
|
val memWriteIn = Input(Bool())
|
||||||
val memWriteOut = Output(Bool())
|
val memWriteOut = Output(Bool())
|
||||||
|
|
||||||
val forwardMem = Input(Bool())
|
val forwardMem = Input(new Forwarding)
|
||||||
val forwardMemAddr = Input(UInt(5.W))
|
val forwardWb = Input(new Forwarding)
|
||||||
val forwardMemData = Input(UInt(32.W))
|
val forwardId = Input(new Forwarding)
|
||||||
val forwardWb = Input(Bool())
|
|
||||||
val forwardWbAddr = Input(UInt(5.W))
|
|
||||||
val forwardWbData = Input(UInt(32.W))
|
|
||||||
val forwardId = Input(Bool())
|
|
||||||
val forwardIdAddr = Input(UInt(5.W))
|
|
||||||
val forwardIdData = Input(UInt(32.W))
|
|
||||||
})
|
})
|
||||||
|
|
||||||
val isOp1RValue = RegInit(Bool(), false.B)
|
val isOp1RValue = RegInit(Bool(), false.B)
|
||||||
|
@ -64,56 +58,56 @@ class IDBarrier extends MultiIOModule {
|
||||||
val op1 = RegInit(SInt(32.W), 0.S)
|
val op1 = RegInit(SInt(32.W), 0.S)
|
||||||
op1 := io.op1in
|
op1 := io.op1in
|
||||||
io.op1out := Mux(
|
io.op1out := Mux(
|
||||||
io.forwardMem && isOp1RValue && r1Address === io.forwardMemAddr,
|
isOp1RValue && io.forwardMem.valid && r1Address === io.forwardMem.writeAddr,
|
||||||
io.forwardMemData.asSInt(),
|
io.forwardMem.writeData.asSInt(),
|
||||||
Mux(
|
Mux(
|
||||||
io.forwardWb && isOp1RValue && r1Address === io.forwardWbAddr,
|
isOp1RValue && io.forwardWb.valid && r1Address === io.forwardWb.writeAddr,
|
||||||
io.forwardWbData.asSInt(),
|
io.forwardWb.writeData.asSInt(),
|
||||||
Mux(
|
Mux(
|
||||||
io.forwardId && isOp1RValue && r1Address === io.forwardIdAddr,
|
isOp1RValue && io.forwardId.valid && r1Address === io.forwardId.writeAddr,
|
||||||
io.forwardIdData.asSInt(),
|
io.forwardId.writeData.asSInt(),
|
||||||
op1.asSInt(),
|
op1.asSInt(),
|
||||||
)))
|
)))
|
||||||
|
|
||||||
val op2 = RegInit(SInt(32.W), 0.S)
|
val op2 = RegInit(SInt(32.W), 0.S)
|
||||||
op2 := io.op2in
|
op2 := io.op2in
|
||||||
io.op2out := Mux(
|
io.op2out := Mux(
|
||||||
io.forwardMem && isOp2RValue && r2Address === io.forwardMemAddr,
|
isOp2RValue && io.forwardMem.valid && r2Address === io.forwardMem.writeAddr,
|
||||||
io.forwardMemData.asSInt(),
|
io.forwardMem.writeData.asSInt(),
|
||||||
Mux(
|
Mux(
|
||||||
io.forwardWb && isOp2RValue && r2Address === io.forwardWbAddr,
|
isOp2RValue && io.forwardWb.valid && r2Address === io.forwardWb.writeAddr,
|
||||||
io.forwardWbData.asSInt(),
|
io.forwardWb.writeData.asSInt(),
|
||||||
Mux(
|
Mux(
|
||||||
io.forwardId && isOp2RValue && r2Address === io.forwardIdAddr,
|
isOp2RValue && io.forwardId.valid && r2Address === io.forwardId.writeAddr,
|
||||||
io.forwardIdData.asSInt(),
|
io.forwardId.writeData.asSInt(),
|
||||||
op2.asSInt(),
|
op2.asSInt(),
|
||||||
)))
|
)))
|
||||||
|
|
||||||
val r1Value = RegInit(UInt(32.W), 0.U)
|
val r1Value = RegInit(UInt(32.W), 0.U)
|
||||||
r1Value := io.r1ValueIn
|
r1Value := io.r1ValueIn
|
||||||
io.r1ValueOut := Mux(
|
io.r1ValueOut := Mux(
|
||||||
io.forwardMem && r1Address === io.forwardMemAddr,
|
io.forwardMem.valid && r1Address === io.forwardMem.writeAddr,
|
||||||
io.forwardMemData,
|
io.forwardMem.writeData,
|
||||||
Mux(
|
Mux(
|
||||||
io.forwardWb && r1Address === io.forwardWbAddr,
|
io.forwardWb.valid && r1Address === io.forwardWb.writeAddr,
|
||||||
io.forwardWbData,
|
io.forwardWb.writeData,
|
||||||
Mux(
|
Mux(
|
||||||
io.forwardId && r1Address === io.forwardIdAddr,
|
io.forwardId.valid && r1Address === io.forwardId.writeAddr,
|
||||||
io.forwardIdData,
|
io.forwardId.writeData,
|
||||||
r1Value,
|
r1Value,
|
||||||
)))
|
)))
|
||||||
|
|
||||||
val r2Value = RegInit(UInt(32.W), 0.U)
|
val r2Value = RegInit(UInt(32.W), 0.U)
|
||||||
r2Value := io.r2ValueIn
|
r2Value := io.r2ValueIn
|
||||||
io.r2ValueOut := Mux(
|
io.r2ValueOut := Mux(
|
||||||
io.forwardMem && r2Address === io.forwardMemAddr,
|
io.forwardMem.valid && r2Address === io.forwardMem.writeAddr,
|
||||||
io.forwardMemData,
|
io.forwardMem.writeData,
|
||||||
Mux(
|
Mux(
|
||||||
io.forwardWb && r2Address === io.forwardWbAddr,
|
io.forwardWb.valid && r2Address === io.forwardWb.writeAddr,
|
||||||
io.forwardWbData,
|
io.forwardWb.writeData,
|
||||||
Mux(
|
Mux(
|
||||||
io.forwardId && r2Address === io.forwardIdAddr,
|
io.forwardId.valid && r2Address === io.forwardId.writeAddr,
|
||||||
io.forwardIdData,
|
io.forwardId.writeData,
|
||||||
r2Value,
|
r2Value,
|
||||||
)))
|
)))
|
||||||
|
|
||||||
|
|
|
@ -12,15 +12,9 @@ class MEMBarrier extends MultiIOModule {
|
||||||
val writeEnableIn = Input(Bool())
|
val writeEnableIn = Input(Bool())
|
||||||
val writeEnableOut = Output(Bool())
|
val writeEnableOut = Output(Bool())
|
||||||
val memRead = Input(Bool())
|
val memRead = Input(Bool())
|
||||||
val forwardMem = Output(Bool())
|
val forwardMem = Output(new Forwarding)
|
||||||
val forwardMemAddr = Output(UInt(5.W))
|
val forwardWb = Output(new Forwarding)
|
||||||
val forwardMemData = Output(UInt(32.W))
|
val forwardId = Output(new Forwarding)
|
||||||
val forwardWb = Output(Bool())
|
|
||||||
val forwardWbAddr = Output(UInt(5.W))
|
|
||||||
val forwardWbData = Output(UInt(32.W))
|
|
||||||
val forwardId = Output(Bool())
|
|
||||||
val forwardIdAddr = Output(UInt(5.W))
|
|
||||||
val forwardIdData = Output(UInt(32.W))
|
|
||||||
})
|
})
|
||||||
|
|
||||||
val memRead = RegInit(Bool(), false.B)
|
val memRead = RegInit(Bool(), false.B)
|
||||||
|
@ -38,13 +32,13 @@ class MEMBarrier extends MultiIOModule {
|
||||||
writeEnable := io.writeEnableIn
|
writeEnable := io.writeEnableIn
|
||||||
io.writeEnableOut := writeEnable
|
io.writeEnableOut := writeEnable
|
||||||
|
|
||||||
io.forwardMem := io.writeEnableIn && !io.memRead
|
io.forwardMem.write := io.writeEnableIn && !io.memRead
|
||||||
io.forwardMemAddr := io.writeAddrIn
|
io.forwardMem.writeAddr := io.writeAddrIn
|
||||||
io.forwardMemData := io.dataIn
|
io.forwardMem.writeData := io.dataIn
|
||||||
|
|
||||||
io.forwardWb := writeEnable
|
io.forwardWb.write := writeEnable
|
||||||
io.forwardWbAddr := writeAddr
|
io.forwardWb.writeAddr := writeAddr
|
||||||
io.forwardWbData := io.dataOut
|
io.forwardWb.writeData := io.dataOut
|
||||||
|
|
||||||
val forwardId = RegInit(Bool(), false.B)
|
val forwardId = RegInit(Bool(), false.B)
|
||||||
forwardId := writeEnable
|
forwardId := writeEnable
|
||||||
|
@ -53,7 +47,14 @@ class MEMBarrier extends MultiIOModule {
|
||||||
val forwardIdData = RegInit(UInt(32.W), 0.U)
|
val forwardIdData = RegInit(UInt(32.W), 0.U)
|
||||||
forwardIdData := io.dataOut
|
forwardIdData := io.dataOut
|
||||||
|
|
||||||
io.forwardId := forwardId
|
io.forwardId.write := forwardId
|
||||||
io.forwardIdAddr := forwardIdAddr
|
io.forwardId.writeAddr := forwardIdAddr
|
||||||
io.forwardIdData := forwardIdData
|
io.forwardId.writeData := forwardIdData
|
||||||
|
}
|
||||||
|
|
||||||
|
class Forwarding extends Bundle {
|
||||||
|
val writeAddr = UInt(5.W)
|
||||||
|
val writeData = UInt(32.W)
|
||||||
|
val write = Bool()
|
||||||
|
def valid = write && (writeAddr =/= 0.U)
|
||||||
}
|
}
|
||||||
|
|
5
src/test/resources/tests/addload.s
Normal file
5
src/test/resources/tests/addload.s
Normal file
|
@ -0,0 +1,5 @@
|
||||||
|
main:
|
||||||
|
addi a5,a5,2
|
||||||
|
lw a4,-36(s0)
|
||||||
|
add a5,a4,a5
|
||||||
|
done
|
|
@ -4,5 +4,4 @@ main:
|
||||||
loop:
|
loop:
|
||||||
addi x2, x2, 1
|
addi x2, x2, 1
|
||||||
blt x2, x1, loop
|
blt x2, x1, loop
|
||||||
nop
|
|
||||||
done
|
done
|
18
src/test/resources/tests/fucked.s
Normal file
18
src/test/resources/tests/fucked.s
Normal file
|
@ -0,0 +1,18 @@
|
||||||
|
main:
|
||||||
|
addi x2, x2, 0
|
||||||
|
j loop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
|
||||||
|
|
||||||
|
loop:
|
||||||
|
addi x1, x1, 32
|
||||||
|
blt x1, x2, loop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
nop
|
||||||
|
j end
|
||||||
|
|
||||||
|
end:
|
||||||
|
done
|
|
@ -19,7 +19,7 @@ import LogParser._
|
||||||
|
|
||||||
object Manifest {
|
object Manifest {
|
||||||
|
|
||||||
val singleTest = "branch.s"
|
val singleTest = "fucked.s"
|
||||||
|
|
||||||
val nopPadded = false
|
val nopPadded = false
|
||||||
|
|
||||||
|
|
Loading…
Add table
Add a link
Reference in a new issue