From 1eefeca2d6c2fd4617eb43d823e26007024a3a17 Mon Sep 17 00:00:00 2001 From: Sebastian Bugge Date: Tue, 5 Nov 2024 14:13:15 +0100 Subject: [PATCH] Simplify forwarding. --- src/main/scala/CPU.scala | 8 ---- src/main/scala/IDBarrier.scala | 60 ++++++++++++++---------------- src/main/scala/MEMBarrier.scala | 37 +++++++++--------- src/test/resources/tests/addload.s | 5 +++ src/test/resources/tests/branch.s | 1 - src/test/resources/tests/fucked.s | 18 +++++++++ src/test/scala/Manifest.scala | 2 +- 7 files changed, 70 insertions(+), 61 deletions(-) create mode 100644 src/test/resources/tests/addload.s create mode 100644 src/test/resources/tests/fucked.s diff --git a/src/main/scala/CPU.scala b/src/main/scala/CPU.scala index dc57158..a34dfc7 100644 --- a/src/main/scala/CPU.scala +++ b/src/main/scala/CPU.scala @@ -117,17 +117,9 @@ class CPU extends MultiIOModule { IF.io.branchAddress := EXBarrier.ALUResultOut // Forwarding - IDBarrier.forwardMemData := MEMBarrier.forwardMemData IDBarrier.forwardMem := MEMBarrier.forwardMem - IDBarrier.forwardMemAddr := MEMBarrier.forwardMemAddr - - IDBarrier.forwardWbData := MEMBarrier.forwardWbData IDBarrier.forwardWb := MEMBarrier.forwardWb - IDBarrier.forwardWbAddr := MEMBarrier.forwardWbAddr - - IDBarrier.forwardIdData := MEMBarrier.forwardIdData IDBarrier.forwardId := MEMBarrier.forwardId - IDBarrier.forwardIdAddr := MEMBarrier.forwardIdAddr // Stall IF.io.stall := ID.io.stall diff --git a/src/main/scala/IDBarrier.scala b/src/main/scala/IDBarrier.scala index cb9c7e8..fe0ee47 100644 --- a/src/main/scala/IDBarrier.scala +++ b/src/main/scala/IDBarrier.scala @@ -37,15 +37,9 @@ class IDBarrier extends MultiIOModule { val memWriteIn = Input(Bool()) val memWriteOut = Output(Bool()) - val forwardMem = Input(Bool()) - val forwardMemAddr = Input(UInt(5.W)) - val forwardMemData = Input(UInt(32.W)) - val forwardWb = Input(Bool()) - val forwardWbAddr = Input(UInt(5.W)) - val forwardWbData = Input(UInt(32.W)) - val forwardId = Input(Bool()) - val forwardIdAddr = Input(UInt(5.W)) - val forwardIdData = Input(UInt(32.W)) + val forwardMem = Input(new Forwarding) + val forwardWb = Input(new Forwarding) + val forwardId = Input(new Forwarding) }) val isOp1RValue = RegInit(Bool(), false.B) @@ -64,56 +58,56 @@ class IDBarrier extends MultiIOModule { val op1 = RegInit(SInt(32.W), 0.S) op1 := io.op1in io.op1out := Mux( - io.forwardMem && isOp1RValue && r1Address === io.forwardMemAddr, - io.forwardMemData.asSInt(), + isOp1RValue && io.forwardMem.valid && r1Address === io.forwardMem.writeAddr, + io.forwardMem.writeData.asSInt(), Mux( - io.forwardWb && isOp1RValue && r1Address === io.forwardWbAddr, - io.forwardWbData.asSInt(), + isOp1RValue && io.forwardWb.valid && r1Address === io.forwardWb.writeAddr, + io.forwardWb.writeData.asSInt(), Mux( - io.forwardId && isOp1RValue && r1Address === io.forwardIdAddr, - io.forwardIdData.asSInt(), + isOp1RValue && io.forwardId.valid && r1Address === io.forwardId.writeAddr, + io.forwardId.writeData.asSInt(), op1.asSInt(), ))) val op2 = RegInit(SInt(32.W), 0.S) op2 := io.op2in io.op2out := Mux( - io.forwardMem && isOp2RValue && r2Address === io.forwardMemAddr, - io.forwardMemData.asSInt(), + isOp2RValue && io.forwardMem.valid && r2Address === io.forwardMem.writeAddr, + io.forwardMem.writeData.asSInt(), Mux( - io.forwardWb && isOp2RValue && r2Address === io.forwardWbAddr, - io.forwardWbData.asSInt(), + isOp2RValue && io.forwardWb.valid && r2Address === io.forwardWb.writeAddr, + io.forwardWb.writeData.asSInt(), Mux( - io.forwardId && isOp2RValue && r2Address === io.forwardIdAddr, - io.forwardIdData.asSInt(), + isOp2RValue && io.forwardId.valid && r2Address === io.forwardId.writeAddr, + io.forwardId.writeData.asSInt(), op2.asSInt(), ))) val r1Value = RegInit(UInt(32.W), 0.U) r1Value := io.r1ValueIn io.r1ValueOut := Mux( - io.forwardMem && r1Address === io.forwardMemAddr, - io.forwardMemData, + io.forwardMem.valid && r1Address === io.forwardMem.writeAddr, + io.forwardMem.writeData, Mux( - io.forwardWb && r1Address === io.forwardWbAddr, - io.forwardWbData, + io.forwardWb.valid && r1Address === io.forwardWb.writeAddr, + io.forwardWb.writeData, Mux( - io.forwardId && r1Address === io.forwardIdAddr, - io.forwardIdData, + io.forwardId.valid && r1Address === io.forwardId.writeAddr, + io.forwardId.writeData, r1Value, ))) val r2Value = RegInit(UInt(32.W), 0.U) r2Value := io.r2ValueIn io.r2ValueOut := Mux( - io.forwardMem && r2Address === io.forwardMemAddr, - io.forwardMemData, + io.forwardMem.valid && r2Address === io.forwardMem.writeAddr, + io.forwardMem.writeData, Mux( - io.forwardWb && r2Address === io.forwardWbAddr, - io.forwardWbData, + io.forwardWb.valid && r2Address === io.forwardWb.writeAddr, + io.forwardWb.writeData, Mux( - io.forwardId && r2Address === io.forwardIdAddr, - io.forwardIdData, + io.forwardId.valid && r2Address === io.forwardId.writeAddr, + io.forwardId.writeData, r2Value, ))) diff --git a/src/main/scala/MEMBarrier.scala b/src/main/scala/MEMBarrier.scala index 57e6fc1..1187a9f 100644 --- a/src/main/scala/MEMBarrier.scala +++ b/src/main/scala/MEMBarrier.scala @@ -12,15 +12,9 @@ class MEMBarrier extends MultiIOModule { val writeEnableIn = Input(Bool()) val writeEnableOut = Output(Bool()) val memRead = Input(Bool()) - val forwardMem = Output(Bool()) - val forwardMemAddr = Output(UInt(5.W)) - val forwardMemData = Output(UInt(32.W)) - val forwardWb = Output(Bool()) - val forwardWbAddr = Output(UInt(5.W)) - val forwardWbData = Output(UInt(32.W)) - val forwardId = Output(Bool()) - val forwardIdAddr = Output(UInt(5.W)) - val forwardIdData = Output(UInt(32.W)) + val forwardMem = Output(new Forwarding) + val forwardWb = Output(new Forwarding) + val forwardId = Output(new Forwarding) }) val memRead = RegInit(Bool(), false.B) @@ -38,13 +32,13 @@ class MEMBarrier extends MultiIOModule { writeEnable := io.writeEnableIn io.writeEnableOut := writeEnable - io.forwardMem := io.writeEnableIn && !io.memRead - io.forwardMemAddr := io.writeAddrIn - io.forwardMemData := io.dataIn + io.forwardMem.write := io.writeEnableIn && !io.memRead + io.forwardMem.writeAddr := io.writeAddrIn + io.forwardMem.writeData := io.dataIn - io.forwardWb := writeEnable - io.forwardWbAddr := writeAddr - io.forwardWbData := io.dataOut + io.forwardWb.write := writeEnable + io.forwardWb.writeAddr := writeAddr + io.forwardWb.writeData := io.dataOut val forwardId = RegInit(Bool(), false.B) forwardId := writeEnable @@ -53,7 +47,14 @@ class MEMBarrier extends MultiIOModule { val forwardIdData = RegInit(UInt(32.W), 0.U) forwardIdData := io.dataOut - io.forwardId := forwardId - io.forwardIdAddr := forwardIdAddr - io.forwardIdData := forwardIdData + io.forwardId.write := forwardId + io.forwardId.writeAddr := forwardIdAddr + io.forwardId.writeData := forwardIdData +} + +class Forwarding extends Bundle { + val writeAddr = UInt(5.W) + val writeData = UInt(32.W) + val write = Bool() + def valid = write && (writeAddr =/= 0.U) } diff --git a/src/test/resources/tests/addload.s b/src/test/resources/tests/addload.s new file mode 100644 index 0000000..ea26489 --- /dev/null +++ b/src/test/resources/tests/addload.s @@ -0,0 +1,5 @@ +main: + addi a5,a5,2 + lw a4,-36(s0) + add a5,a4,a5 + done \ No newline at end of file diff --git a/src/test/resources/tests/branch.s b/src/test/resources/tests/branch.s index 64d56ef..0761396 100644 --- a/src/test/resources/tests/branch.s +++ b/src/test/resources/tests/branch.s @@ -4,5 +4,4 @@ main: loop: addi x2, x2, 1 blt x2, x1, loop - nop done \ No newline at end of file diff --git a/src/test/resources/tests/fucked.s b/src/test/resources/tests/fucked.s new file mode 100644 index 0000000..2661c5e --- /dev/null +++ b/src/test/resources/tests/fucked.s @@ -0,0 +1,18 @@ +main: + addi x2, x2, 0 + j loop + nop + nop + + +loop: + addi x1, x1, 32 + blt x1, x2, loop + nop + nop + nop + nop + j end + +end: + done diff --git a/src/test/scala/Manifest.scala b/src/test/scala/Manifest.scala index d10ed8a..01665d6 100644 --- a/src/test/scala/Manifest.scala +++ b/src/test/scala/Manifest.scala @@ -19,7 +19,7 @@ import LogParser._ object Manifest { - val singleTest = "branch.s" + val singleTest = "fucked.s" val nopPadded = false