kaholaz/TDT4255
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Simplify forwarding.

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This commit is contained in:
Sebastian Bugge 2024-11-05 14:13:15 +01:00
parent 804e1ed2e6
commit 1eefeca2d6
Signed by: kaholaz
GPG key ID: 2EFFEDEE03519691
7 changed files with 70 additions and 61 deletions
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60
src/main/scala/IDBarrier.scala
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@ -37,15 +37,9 @@ class IDBarrier extends MultiIOModule {
val memWriteIn = Input(Bool())
val memWriteOut = Output(Bool())
val forwardMem = Input(Bool())
val forwardMemAddr = Input(UInt(5.W))
val forwardMemData = Input(UInt(32.W))
val forwardWb = Input(Bool())
val forwardWbAddr = Input(UInt(5.W))
val forwardWbData = Input(UInt(32.W))
val forwardId = Input(Bool())
val forwardIdAddr = Input(UInt(5.W))
val forwardIdData = Input(UInt(32.W))
val forwardMem = Input(new Forwarding)
val forwardWb = Input(new Forwarding)
val forwardId = Input(new Forwarding)
})
val isOp1RValue = RegInit(Bool(), false.B)
@ -64,56 +58,56 @@ class IDBarrier extends MultiIOModule {
val op1 = RegInit(SInt(32.W), 0.S)
op1 := io.op1in
io.op1out := Mux(
io.forwardMem && isOp1RValue && r1Address === io.forwardMemAddr,
io.forwardMemData.asSInt(),
isOp1RValue && io.forwardMem.valid && r1Address === io.forwardMem.writeAddr,
io.forwardMem.writeData.asSInt(),
Mux(
io.forwardWb && isOp1RValue && r1Address === io.forwardWbAddr,
io.forwardWbData.asSInt(),
isOp1RValue && io.forwardWb.valid && r1Address === io.forwardWb.writeAddr,
io.forwardWb.writeData.asSInt(),
Mux(
io.forwardId && isOp1RValue && r1Address === io.forwardIdAddr,
io.forwardIdData.asSInt(),
isOp1RValue && io.forwardId.valid && r1Address === io.forwardId.writeAddr,
io.forwardId.writeData.asSInt(),
op1.asSInt(),
)))
val op2 = RegInit(SInt(32.W), 0.S)
op2 := io.op2in
io.op2out := Mux(
io.forwardMem && isOp2RValue && r2Address === io.forwardMemAddr,
io.forwardMemData.asSInt(),
isOp2RValue && io.forwardMem.valid && r2Address === io.forwardMem.writeAddr,
io.forwardMem.writeData.asSInt(),
Mux(
io.forwardWb && isOp2RValue && r2Address === io.forwardWbAddr,
io.forwardWbData.asSInt(),
isOp2RValue && io.forwardWb.valid && r2Address === io.forwardWb.writeAddr,
io.forwardWb.writeData.asSInt(),
Mux(
io.forwardId && isOp2RValue && r2Address === io.forwardIdAddr,
io.forwardIdData.asSInt(),
isOp2RValue && io.forwardId.valid && r2Address === io.forwardId.writeAddr,
io.forwardId.writeData.asSInt(),
op2.asSInt(),
)))
val r1Value = RegInit(UInt(32.W), 0.U)
r1Value := io.r1ValueIn
io.r1ValueOut := Mux(
io.forwardMem && r1Address === io.forwardMemAddr,
io.forwardMemData,
io.forwardMem.valid && r1Address === io.forwardMem.writeAddr,
io.forwardMem.writeData,
Mux(
io.forwardWb && r1Address === io.forwardWbAddr,
io.forwardWbData,
io.forwardWb.valid && r1Address === io.forwardWb.writeAddr,
io.forwardWb.writeData,
Mux(
io.forwardId && r1Address === io.forwardIdAddr,
io.forwardIdData,
io.forwardId.valid && r1Address === io.forwardId.writeAddr,
io.forwardId.writeData,
r1Value,
)))
val r2Value = RegInit(UInt(32.W), 0.U)
r2Value := io.r2ValueIn
io.r2ValueOut := Mux(
io.forwardMem && r2Address === io.forwardMemAddr,
io.forwardMemData,
io.forwardMem.valid && r2Address === io.forwardMem.writeAddr,
io.forwardMem.writeData,
Mux(
io.forwardWb && r2Address === io.forwardWbAddr,
io.forwardWbData,
io.forwardWb.valid && r2Address === io.forwardWb.writeAddr,
io.forwardWb.writeData,
Mux(
io.forwardId && r2Address === io.forwardIdAddr,
io.forwardIdData,
io.forwardId.valid && r2Address === io.forwardId.writeAddr,
io.forwardId.writeData,
r2Value,
)))