52 lines
1.4 KiB
Scala
52 lines
1.4 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.experimental.MultiIOModule
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/**
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* This module is finished and does not need to be modified to complete your fivestage.
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*
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* When setup is enabled data is written to the instruction memory.
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* In normal operation this memory is write only (no self modifying code)
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*/
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class IMEM() extends MultiIOModule {
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// Don't touch
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val testHarness = IO(
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new Bundle {
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val setupSignals = Input(new IMEMsetupSignals)
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val requestedAddress = Output(UInt())
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}
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)
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val io = IO(
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new Bundle {
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val instructionAddress = Input(UInt(32.W))
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val instruction = Output(UInt(32.W))
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})
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/**
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SyncReadMem will output the value of the address signal set in the previous cycle.
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*/
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val instructions = SyncReadMem(4096, UInt(32.W))
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// The address we want to read at during operation. During setup it acts as a write address
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// leading to the somewhat uninformative name shown here.
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val addressSource = Wire(UInt(32.W))
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testHarness.requestedAddress := io.instructionAddress
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when(testHarness.setupSignals.setup){
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addressSource := testHarness.setupSignals.address
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}.otherwise {
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addressSource := io.instructionAddress
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}
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// For loading data
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when(testHarness.setupSignals.setup){
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instructions(addressSource) := testHarness.setupSignals.instruction
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}
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io.instruction := instructions(addressSource)
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}
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