58 lines
1.5 KiB
Scala
58 lines
1.5 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.experimental.MultiIOModule
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class IDBarrier extends MultiIOModule {
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val io = IO(
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new Bundle {
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val op1in = Input(SInt(32.W))
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val op1out = Output(SInt(32.W))
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val op2in = Input(SInt(32.W))
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val op2out = Output(SInt(32.W))
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val r2ValueIn = Input(UInt(32.W))
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val r2ValueOut = Output(UInt(32.W))
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val ALUopIn = Input(UInt(4.W))
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val ALUopOut = Output(UInt(4.W))
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val writeAddrIn = Input(UInt(5.W))
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val writeAddrOut = Output(UInt(5.W))
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val writeEnableIn = Input(Bool())
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val writeEnableOut = Output(Bool())
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val memReadIn = Input(Bool())
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val memReadOut = Output(Bool())
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val memWriteIn = Input(Bool())
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val memWriteOut = Output(Bool())
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})
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val op1 = RegInit(SInt(32.W), 0.S)
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op1 := io.op1in
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io.op1out := op1
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val op2 = RegInit(SInt(32.W), 0.S)
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op2 := io.op2in
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io.op2out := op2
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val r2Value = RegInit(UInt(32.W), 0.U)
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r2Value := io.r2ValueIn
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io.r2ValueOut := r2Value
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val ALUop = RegInit(UInt(4.W), 0.U)
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ALUop := io.ALUopIn
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io.ALUopOut := ALUop
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val writeAddr = RegInit(UInt(5.W), 0.U)
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writeAddr := io.writeAddrIn
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io.writeAddrOut := writeAddr
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val writeEnable = RegInit(Bool(), false.B)
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writeEnable := io.writeEnableIn
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io.writeEnableOut := writeEnable
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val memRead = RegInit(Bool(), false.B)
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memRead := io.memReadIn
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io.memReadOut := memRead
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val memWrite = RegInit(Bool(), false.B)
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memWrite := io.memWriteIn
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io.memWriteOut := memWrite
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}
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