82 lines
3 KiB
Scala
82 lines
3 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.util.BitPat
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import chisel3.util.ListLookup
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/**
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* This module is mostly done, but you will have to fill in the blanks in opcodeMap.
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* You may want to add more signals to be decoded in this module depending on your
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* design if you so desire.
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*
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* In the "classic" 5 stage decoder signals such as op1select and immType
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* are not included, however I have added them to my design, and similarily you might
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* find it useful to add more
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*/
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class Decoder() extends Module {
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val io = IO(new Bundle {
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val instruction = Input(new Instruction)
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val controlSignals = Output(new ControlSignals)
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val branchType = Output(UInt(3.W))
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val op1Select = Output(UInt(1.W))
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val op2Select = Output(UInt(1.W))
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val immType = Output(UInt(3.W))
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val ALUop = Output(UInt(4.W))
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})
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import lookup._
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import Op1Select._
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import Op2Select._
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import branchType._
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import ImmFormat._
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val N = 0.asUInt(1.W)
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val Y = 1.asUInt(1.W)
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/**
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* In scala we sometimes (ab)use the `->` operator to create tuples.
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* The reason for this is that it serves as convenient sugar to make maps.
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*
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* This doesn't matter to you, just fill in the blanks in the style currently
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* used, I just want to demystify some of the scala magic.
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*
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* `a -> b` == `(a, b)` == `Tuple2(a, b)`
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*/
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val opcodeMap: Array[(BitPat, List[UInt])] = Array(
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// signal memToReg, regWrite, memRead, memWrite, branch, jump, branchType, Op1Select, Op2Select, ImmSelect, ALUOp
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LW -> List(Y, Y, Y, N, N, N, branchType.DC, rs1, imm, ITYPE, ALUOps.ADD),
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SW -> List(N, N, N, Y, N, N, branchType.DC, rs1, imm, STYPE, ALUOps.ADD),
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ADD -> List(N, Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.ADD),
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SUB -> List(N, Y, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.SUB),
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/**
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TODO: Fill in the blanks
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*/
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)
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val NOP = List(N, N, N, N, N, N, branchType.DC, rs1, rs2, ImmFormat.DC, ALUOps.DC)
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val decodedControlSignals = ListLookup(
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io.instruction.asUInt(),
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NOP,
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opcodeMap)
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io.controlSignals.memToReg := decodedControlSignals(0)
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io.controlSignals.regWrite := decodedControlSignals(1)
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io.controlSignals.memRead := decodedControlSignals(2)
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io.controlSignals.memWrite := decodedControlSignals(3)
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io.controlSignals.branch := decodedControlSignals(4)
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io.controlSignals.jump := decodedControlSignals(5)
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io.branchType := decodedControlSignals(6)
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io.op1Select := decodedControlSignals(7)
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io.op2Select := decodedControlSignals(8)
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io.immType := decodedControlSignals(9)
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io.ALUop := decodedControlSignals(10)
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}
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