51 lines
1.2 KiB
Scala
51 lines
1.2 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.util._
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import chisel3.experimental.MultiIOModule
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class MemoryFetch() extends MultiIOModule {
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// Don't touch the test harness
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val testHarness = IO(
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new Bundle {
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val DMEMsetup = Input(new DMEMsetupSignals)
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val DMEMpeek = Output(UInt(32.W))
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val testUpdates = Output(new MemUpdates)
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})
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val io = IO(
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new Bundle {
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val ALUResult = Input(UInt(32.W))
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val writeData = Input(UInt(32.W))
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val readMem = Input(Bool())
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val writeMem = Input(Bool())
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val dataOut = Output(UInt(32.W))
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val jump = Input(Bool())
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val returnAddr = Input(UInt(32.W))
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})
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val DMEM = Module(new DMEM)
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/**
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* Setup. You should not change this code
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*/
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DMEM.testHarness.setup := testHarness.DMEMsetup
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testHarness.DMEMpeek := DMEM.io.dataOut
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testHarness.testUpdates := DMEM.testHarness.testUpdates
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/**
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* Your code here.
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*/
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DMEM.io.dataIn := io.writeData
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DMEM.io.writeEnable := io.writeMem
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DMEM.io.dataAddress := io.ALUResult
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val readMem = RegInit(Bool(), false.B)
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readMem := io.readMem
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io.dataOut := Mux(readMem, DMEM.io.dataOut, Mux(io.jump, io.returnAddr, io.ALUResult))
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}
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