59 lines
1.2 KiB
Scala
59 lines
1.2 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.experimental.MultiIOModule
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class InstructionFetch extends MultiIOModule {
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// Don't touch
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val testHarness = IO(
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new Bundle {
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val IMEMsetup = Input(new IMEMsetupSignals)
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val PC = Output(UInt())
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}
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)
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/**
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* TODO: Add signals for handling events such as jumps
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*/
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val io = IO(
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new Bundle {
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val PC = Output(UInt())
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})
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val IMEM = Module(new IMEM)
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val PC = RegInit(UInt(32.W), 0.U)
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/**
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* Setup. You should not change this code
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*/
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IMEM.testHarness.setupSignals := testHarness.IMEMsetup
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testHarness.PC := IMEM.testHarness.requestedAddress
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/**
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* TODO: Your code here.
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*
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* You should expand on or rewrite the code below.
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*/
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io.PC := PC
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IMEM.io.instructionAddress := PC
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PC := PC + 4.U
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val instruction = Wire(new Instruction)
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instruction := IMEM.io.instruction.asTypeOf(new Instruction)
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/**
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* Setup. You should not change this code
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*/
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when(testHarness.IMEMsetup.setup) {
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PC := 0.U
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// TODO: You must set the instruction to Instruction.NOP here.
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// throw new Exception("Just making sure you're seeing the line above")
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}
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}
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