49 lines
1.1 KiB
Scala
49 lines
1.1 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.util.{ BitPat, MuxCase }
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import chisel3.experimental.MultiIOModule
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class InstructionDecode extends MultiIOModule {
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// Don't touch the test harness
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val testHarness = IO(
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new Bundle {
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val registerSetup = Input(new RegisterSetupSignals)
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val registerPeek = Output(UInt(32.W))
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val testUpdates = Output(new RegisterUpdates)
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})
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val io = IO(
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new Bundle {
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/**
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* TODO: Your code here.
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*/
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}
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)
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val registers = Module(new Registers)
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val decoder = Module(new Decoder).io
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/**
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* Setup. You should not change this code
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*/
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registers.testHarness.setup := testHarness.registerSetup
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testHarness.registerPeek := registers.io.readData1
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testHarness.testUpdates := registers.testHarness.testUpdates
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/**
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* TODO: Your code here.
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*/
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registers.io.readAddress1 := 0.U
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registers.io.readAddress2 := 0.U
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registers.io.writeEnable := false.B
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registers.io.writeAddress := 0.U
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registers.io.writeData := 0.U
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decoder.instruction := 0.U.asTypeOf(new Instruction)
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}
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