51 lines
No EOL
1.7 KiB
Scala
51 lines
No EOL
1.7 KiB
Scala
package FiveStage
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import Chisel.MuxLookup
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import chisel3._
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import chisel3.util.{BitPat, MuxCase}
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import chisel3.experimental.MultiIOModule
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class Execute extends MultiIOModule {
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val io = IO(
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new Bundle {
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val op1 = Input(SInt(32.W))
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val op2 = Input(SInt(32.W))
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val rs1ValueIn = Input(SInt(32.W))
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val rs2ValueIn = Input(SInt(32.W))
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val rs2ValueOut = Output(SInt(32.W))
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val branchType = Input(UInt(3.W))
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val branch = Output(Bool())
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val ALUOp = Input(UInt(4.W))
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val ALUResult = Output(SInt(32.W))
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}
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)
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val ALUOpsMap = Array (
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ALUOps.ADD -> (io.op1 + io.op2),
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ALUOps.SUB -> (io.op1 - io.op2),
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ALUOps.AND -> (io.op1 & io.op2),
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ALUOps.OR -> (io.op1 | io.op2),
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ALUOps.XOR -> (io.op1 ^ io.op2),
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ALUOps.SLT -> Mux(io.op1 < io.op2, 1.S, 0.S),
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ALUOps.SLTU -> Mux(io.op1.asUInt() < io.op2.asUInt(), 1.S, 0.S),
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ALUOps.SRA -> (io.op1 >> io.op2(4, 0)),
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ALUOps.SRL -> (io.op1.asUInt() >> io.op2(4, 0)).asSInt(),
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ALUOps.SLL -> (io.op1.asUInt() << io.op2(4, 0)).asSInt(),
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ALUOps.COPY_A -> io.op1,
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ALUOps.COPY_B -> io.op2,
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)
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val BranchALUOpsMap = Array (
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branchType.beq -> (io.rs1ValueIn === io.rs2ValueIn),
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branchType.neq -> !(io.rs1ValueIn === io.rs2ValueIn),
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branchType.lt -> (io.rs1ValueIn < io.rs2ValueIn),
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branchType.gte -> (io.rs1ValueIn >= io.rs2ValueIn),
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branchType.ltu -> (io.rs1ValueIn.asUInt() < io.rs2ValueIn.asUInt()),
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branchType.gteu -> (io.rs1ValueIn.asUInt() >= io.rs2ValueIn.asUInt()),
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branchType.jump -> true.B,
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)
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io.rs2ValueOut := io.rs2ValueIn
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io.branch := MuxLookup(io.branchType, false.B, BranchALUOpsMap)
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io.ALUResult := MuxLookup(io.ALUOp, 0.S(32.W), ALUOpsMap)
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} |