353 lines
14 KiB
Scala
353 lines
14 KiB
Scala
package FiveStage
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import cats.data.Writer
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import cats._
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import cats.data.{ Op => _ }
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import cats.implicits._
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import fansi._
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import Ops._
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import Data._
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import VM._
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import fileUtils._
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object PrintUtils {
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// Minimal typeclass def for being fancy
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trait Fancy[-A] { def s(a: A): fansi.Str }
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implicit class FancyOps[-A](a: A)(implicit ev: Fancy[A]){ def show: fansi.Str = ev.s(a) }
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implicit val DoubleFancy = new Fancy[fansi.Str]{ def s(a: fansi.Str) = a }
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implicit val FancyMonoid = new Monoid[fansi.Str] {
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def empty: fansi.Str = fansi.Str("")
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def combine(self: fansi.Str, that: fansi.Str): fansi.Str = self ++ that
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}
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implicit class ExtraFancy(a: fansi.Str) {
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def leftPad(length: Int): fansi.Str = Str((0 until length).map(_ => ' ').mkString) ++ a
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def replace(from: Char, to: Char): fansi.Str = fansi.Str(a.toString.replace(from, to))
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def padTo(length: Int, pad: Char = ' '): fansi.Str = a ++ (0 until length - a.length).map(_ => pad).mkString
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def trim: fansi.Str = fansi.Str(a.toString.trim)
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}
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implicit val RegFancy = new Fancy[Reg] { def s(r: Reg) = fansi.Str(regNames.canonicalName.lift(r.value).getOrElse("ERROR")) }
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implicit val ImmFancy = new Fancy[Imm] { def s(r: Imm) = Str(r.value.hs) }
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implicit val AddrFancy = new Fancy[Addr]{ def s(r: Addr) = Str(r.value.hs) }
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implicit val ExecutionEventFancy = new Fancy[ExecutionEvent]{
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def s(a: ExecutionEvent): fansi.Str = a match {
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case RegUpdate(reg, word) => Str(s"R(${reg.show}) <- 0x${word.hs}")
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case MemWrite(addr, word) => fansi.Color.Blue(s"M[${addr.show}] <- 0x${word.hs}")
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case MemRead(addr, word) => fansi.Color.Red(f"M[${addr.show}] -> 0x${word.hs}")
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// addr is the target address
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case PcUpdateJALR(addr) => fansi.Color.Green(s"PC updated to ${addr.show} via JALR")
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case PcUpdateJAL(addr) => fansi.Color.Magenta(s"PC updated to ${addr.show} via JAL")
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case PcUpdateB(addr) => fansi.Color.Yellow(s"PC updated to ${addr.show} via Branch")
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}
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}
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implicit val ExecutionTraceEventFancy = new Fancy[ExecutionTraceEvent]{
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def s(a: ExecutionTraceEvent): fansi.Str = a.event.toList match {
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case (h: ExecutionEvent) :: (t: RegUpdate) :: Nil => t.show.padTo(25) ++ h.show
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case (h: MemWrite) :: t :: Nil => t.show.padTo(25) ++ h.show
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case (h: MemRead) :: t :: Nil => t.show.padTo(25) ++ h.show
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case (h: MemWrite) :: Nil => h.show.leftPad(25)
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case (h: MemRead) :: Nil => h.show.leftPad(25)
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case h :: t :: Nil => h.show ++ t.show
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case (h: RegUpdate) :: Nil => h.show
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case h :: Nil => h.show.leftPad(25)
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case _ => Str("")
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}
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}
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implicit val ChiselEventFancy = new Fancy[ChiselEvent]{
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def s(e: ChiselEvent) = e match {
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case ChiselRegEvent(addr, reg, word) => fansi.Str(s"R(${reg.show}) <- ${word.hs}")
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case ChiselMemWriteEvent(addr, memAddr, word) => fansi.Str(s"M[${memAddr.show}] <- ${word.hs}")
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}
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}
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implicit val RegsFancy = new Fancy[Regs]{
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def s(e: Regs) = {
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(0 to 9).map{ idx =>
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val cols = List.range(idx, 32, 10)
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cols.map{ reg =>
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(fansi.Color.Yellow(Reg(reg).show.padTo(5)) ++ Str(e.repr.lift(Reg(reg)).getOrElse(0).hs)).padTo(16)
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}.showN("| ")
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}.toList.showN("\n", "\n", "\n")
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}
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}
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val UNKNOWN = "UNKNOWN"
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def printInstruction(op: Ops.Op, labelMap: Map[Label, Addr]): fansi.Str = op match {
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case op: Branch => fansi.Color.Red(s"B${op.comp}\t${op.rs1.show}, ${op.rs2.show}, ${op.dst.show}\t[${labelMap.lift(op.dst).getOrElse(UNKNOWN)}]")
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case op: Arith => s"${op.op}\t${op.rd.show}, ${op.rs1.show}, ${op.rs2.show}"
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case op: ArithImm => s"${op.op}I\t${op.rd.show}, ${op.rs1.show}, ${op.imm.show}"
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case op: ArithImmShift => s"${op.op}I\t${op.rd.show}, ${op.rs1.show}, ${op.shamt.show}"
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case op: JALR => fansi.Color.Green(s"JALR\t${op.rd.show}, ${op.rs1.show}, ${op.dst.show}\t[${labelMap.lift(op.dst).getOrElse(UNKNOWN)}]")
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case op: JAL => fansi.Color.Magenta(s"JAL\t${op.rd.show}, ${op.dst.show} [${labelMap.lift(op.dst).getOrElse(UNKNOWN)}]")
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case op: LW => s"LW\t${op.rd.show}, ${op.offset.show}(${op.rs1.show})"
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case op: SW => s"SW\t${op.rs2.show}, ${op.offset.show}(${op.rs1.show})"
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case op: LUI => s"LUI\t${op.rd.show}, ${op.imm.show}"
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case op: AUIPC => s"AUIPC\t${op.rd.show}, ${op.imm.show}"
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case DONE => s"DONE"
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}
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implicit class IntPrinters(i: Int) {
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def hs: String = if(i > 65535) f"0x$i%08X" else f"0x$i%04X"
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def binary: String = String.format("%" + 32 + "s", i.toBinaryString)
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.replace(' ', '0').grouped(4)
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.map(x => x + " ").mkString
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}
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def printProgram(vm: VM): String = {
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val withLabels: List[Either[(Addr, Op), (Label, Addr)]] = (vm.imem.toList.map(Left(_)) ::: vm.labelMap.toList.map(Right(_)))
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.sortBy { case Left(x) => x._1.value.toDouble + 0.1; case Right(x) => x._2.value.toDouble }
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withLabels.map{
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case Left((addr, op)) => s"$addr:\t\t${printInstruction(op, vm.labelMap)}"
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case Right((label, addr)) => s"$addr:\t$label:"
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}.mkString("\n","\n","\n")
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}
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def printProgram(p: Program): String = printProgram(p.vm)
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def printBinary(bin: Map[Addr, Int]): String = {
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bin.toList.sortBy(_._1.value).map{ case(addr, op) => s"$addr: ${op.hs}\t--\t${op.binary}" }.mkString("\n","\n","\n")
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}
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def printChiselLogEntry(event: (Addr, List[ChiselEvent])): fansi.Str = {
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val (addr, log) = event
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val events = log match {
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case (h: ChiselRegEvent) :: (t: ChiselMemWriteEvent) :: Nil => h.show.padTo(25, ' ') ++ t.show
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case (h: ChiselMemWriteEvent) :: Nil => h.show.leftPad(25)
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case (h: ChiselRegEvent) :: Nil => h.show
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case _ => fansi.Str("")
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}
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events
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}
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def printVMtrace(trace: List[ExecutionTraceEvent], program: Program): String = {
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val blocks: List[List[(ExecutionTraceEvent, Int)]] = LogParser.splitToBlocks(trace).zipWithIndexNested
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blocks.map{ block =>
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val name = LogParser.guessBlockName(block.map(_._1.pc), program.labelMapReverse)
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val blockString = block.map{ case(event, idx) =>
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Str(s"Step: $idx,").padTo(12) ++
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Str("PC: ") ++
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event.pc.show ++
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Str("\t") ++
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event.show.padTo(70) ++
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printSourceLine(event.pc, program)
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}
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fansi.Color.Yellow(name) ++ Str("\n") ++ blockString.showN("\n")
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}.mkStringN
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}
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def printSourceLine(addr: Addr, program: Program): fansi.Str = program.sourceMap.lift(addr).map(fansi.Str(_)).getOrElse(fansi.Str("???"))
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def printMergedTraces(
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mt: (List[ExecutionTraceEvent], List[CircuitTrace]),
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program: Program
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): List[String] = {
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/**
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* For branch predicting processors we may end up with a spurious block causing a transient
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* desynchronization. Therefore it is necessary to have a certain tolerance before calling a divergence.
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*/
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// TODO: Implement a synchronization test to pinpoint where a desync happens
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// This is not straight forward in the case of processors which perform branch prediction.
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def isSynchronized(desyncs: Int, traces: (List[ExecutionTraceEvent], List[CircuitTrace]) ): Boolean = ???
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def helper(mt: (List[ExecutionTraceEvent], List[CircuitTrace])): List[List[fansi.Str]] = mt match {
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/**
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* VM trace and execution log synchronized, step both
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*/
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case (hVM :: tVM, hC :: tC) if (hVM.pc == hC._1) => {
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val address = hVM.pc
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val chiselLogEntry = printChiselLogEntry(hC)
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val vmEntry = hVM.show
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val sourceLine = printSourceLine(address, program)
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val line = List(address.show, chiselLogEntry, vmEntry, sourceLine)
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line :: helper((tVM, tC))
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}
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/**
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* VM trace and execution log unsynchronized, step only chisel trace
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* Helper is called with (hVM :: tVM) to only step the chisel log.
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*/
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case (hVM :: tVM, hC :: tC) => {
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val address = hC._1
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val chiselLogEntry = printChiselLogEntry(hC)
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val vmEntry = Str("")
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val sourceLine = printSourceLine(address, program)
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val line = List(address.show, chiselLogEntry, vmEntry, sourceLine)
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line :: helper((hVM :: tVM, tC))
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}
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/**
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* The Block contains no more instructions performed by the VM. This
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* happens naturally since 5-stage pipelines will fetch spurious instructions.
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*/
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case (Nil, hC :: tC) => {
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val address = hC._1
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val chiselLogEntry = printChiselLogEntry(hC)
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val vmEntry = fansi.Str("")
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val sourceLine = printSourceLine(address, program)
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val line = List(fansi.Color.LightBlue(address.show), chiselLogEntry, vmEntry, sourceLine)
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line :: helper((Nil, tC))
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}
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/**
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* The Block contains no more instructions performed by the circuit.
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* This happens when the circuit takes a jump the VM does not.
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* This is an error *unless* the circuit has a branch predictor.
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*
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* If you want to you can splice the logs when this happens, but it's typically easy to spot.
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*/
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case (hVM :: tVM, Nil) => {
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val address = hVM.pc
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val chiselLogEntry = fansi.Str("")
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val vmEntry = hVM.show
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val sourceLine = printSourceLine(address, program)
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val line = List(fansi.Color.LightRed(address.show), chiselLogEntry, vmEntry, sourceLine)
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line :: helper((tVM, Nil))
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}
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case (Nil, Nil) => Nil
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}
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def format(triplet: List[fansi.Str]): String = {
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// Ahh, the GNU toolchain and its tabs
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val annoyingTabCharacter = ' '
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triplet match {
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case address :: ch :: vm :: source :: Nil => {
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val vmLine: fansi.Str = vm.padTo(60, ' ')
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val chiselLine: fansi.Str = ch.padTo(50, ' ')
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val sourceLines: fansi.Str = source
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((address ++ Str(":")).padTo(14, ' ') ++ vmLine ++ fansi.Str("| ") ++ chiselLine ++ Str("| ") ++ sourceLines).toString
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}
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case _ => ""
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}
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}
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val blockName = LogParser.guessBlockName(mt._1.map(_.pc), program.labelMapReverse)
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(fansi.Color.Yellow(s"$blockName").padTo(74, ' ').toString ++ "|".padTo(55, ' ') ++ "|") :: helper(mt).map(format)
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}
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def printChiselError(e: Throwable): String = {
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val rawError = """
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|This typically occurs when you forget to wrap a module
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|e.g
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|class MyBundle extends Bundle {
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| val signal = UInt(32.W)
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|}
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|val mySignal = new MyBundle
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| ^^^^ Wrong!
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|should be
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|val mySignal = Wire(new MyBundle)
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""".stripMargin
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def getFiveStageStacktrace(strace: Array[StackTraceElement]): String =
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strace.map(_.toString).filter(_.contains("FiveStage")).toList.take(5).mkStringN
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e match {
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case e: firrtl.passes.CheckInitialization.RefNotInitializedException => {
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s"""
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|##########################################################
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|##########################################################
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|##########################################################
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|Your design has unconnected wires!"
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|error:\n"
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|${e.getMessage}
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|##########################################################
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|##########################################################
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|##########################################################
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""".stripMargin
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}
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case e: chisel3.core.Binding.ExpectedHardwareException => {
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s"""
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|##########################################################
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|##########################################################
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|##########################################################
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|Your design is using raw chisel types!
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|error:\n
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|${e.getMessage}
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|$rawError
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|The error should be here somewhere:
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|${getFiveStageStacktrace(e.getStackTrace)}
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|##########################################################
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|##########################################################
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|##########################################################
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""".stripMargin
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}
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case e: firrtl.passes.PassExceptions => {
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val rawErrorMsg = if(e.getMessage.contains("raw"))
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s"One of the errors was use of raw chisel types. $rawError"
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else
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""
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s"""
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|##########################################################
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|##########################################################
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|##########################################################
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|Your design has multiple errors!
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|error:
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|${e.getMessage}
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|$rawErrorMsg
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|##########################################################
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|##########################################################
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|##########################################################
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""".stripMargin
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}
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case e: Exception => {
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s"""
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|##########################################################
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|##########################################################
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|##########################################################
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|Unexpected Chisel tester error (could be a chisel error I havent accounted for, or a bug in the tester like index out of bounds.)
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|error:
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|${e.getMessage}
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|reduced stacktrace:
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|${getFiveStageStacktrace(e.getStackTrace)}
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|##########################################################
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|##########################################################
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|##########################################################
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""".stripMargin
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}
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}
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}
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def printLogSideBySide(trace: List[ExecutionTraceEvent], chiselTrace: List[CircuitTrace], program: Program): String = {
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import LogParser._
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val traces = mergeTraces(trace, chiselTrace).map(x => printMergedTraces((x), program))
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traces.map(_.mkString("\n")).mkString("\n", "\n--------------------------------------------------------------------------+------------------------------------------------------+-------------------------------\n", "\n")
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}
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}
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