8dc92fb8e1
Pretty sure MemToReg is a MIPS relic, it is redundant so long as all memory reads are put into registers.
124 lines
3 KiB
Scala
124 lines
3 KiB
Scala
package FiveStage
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import chisel3._
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import chisel3.core.Wire
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import chisel3.util.{ BitPat, Cat }
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class Instruction extends Bundle(){
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val instruction = UInt(32.W)
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def opcode = instruction(6, 0)
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def registerRd = instruction(11, 7)
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def funct3 = instruction(14, 12)
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def registerRs1 = instruction(19, 15)
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def registerRs2 = instruction(24, 20)
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def funct7 = instruction(31, 25)
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def funct6 = instruction(26, 31)
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def immediateIType = instruction(31, 20).asSInt
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def immediateSType = Cat(instruction(31, 25), instruction(11,7)).asSInt
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def immediateBType = Cat(instruction(31), instruction(7), instruction(30, 25), instruction(11, 8), 0.U(1.W)).asSInt
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def immediateUType = Cat(instruction(31, 12), 0.U(12.W)).asSInt
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def immediateJType = Cat(instruction(31), instruction(19, 12), instruction(20), instruction(30, 25), instruction(24, 21), 0.U(1.W)).asSInt
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def immediateZType = instruction(19, 15).zext
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def bubble(): Instruction = {
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val bubbled = Wire(new Instruction)
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bubbled.instruction := instruction
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bubbled.instruction(6, 0) := BitPat.bitPatToUInt(BitPat("b0010011"))
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bubbled
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}
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}
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object Instruction {
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def NOP: Instruction = {
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val w = Wire(new Instruction)
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w.instruction := BitPat.bitPatToUInt(BitPat("b00000000000000000000000000010011"))
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w
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}
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}
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class ControlSignals extends Bundle(){
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val regWrite = Bool()
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val memRead = Bool()
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val memWrite = Bool()
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val branch = Bool()
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val jump = Bool()
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}
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object ControlSignals {
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def nop: ControlSignals = {
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val b = Wire(new ControlSignals)
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b.regWrite := false.B
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b.memRead := false.B
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b.memWrite := false.B
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b.branch := false.B
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b.jump := false.B
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b
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}
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}
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object branchType {
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val beq = 0.asUInt(3.W)
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val neq = 1.asUInt(3.W)
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val gte = 2.asUInt(3.W)
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val lt = 3.asUInt(3.W)
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val gteu = 4.asUInt(3.W)
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val ltu = 5.asUInt(3.W)
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val jump = 6.asUInt(3.W)
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val DC = 0.asUInt(3.W)
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}
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/**
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these take the role of the alu source signal.
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Used in the decoder.
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In the solution manual I use these to select signals at the decode stage.
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You can choose to instead do this in the execute stage, and you may forego
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using them altogether.
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*/
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object Op1Select {
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val rs1 = 0.asUInt(1.W)
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val PC = 1.asUInt(1.W)
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val DC = 0.asUInt(1.W)
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}
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object Op2Select {
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val rs2 = 0.asUInt(1.W)
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val imm = 1.asUInt(1.W)
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val DC = 0.asUInt(1.W)
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}
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/**
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Used in the decoder
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*/
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object ImmFormat {
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val ITYPE = 0.asUInt(3.W)
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val STYPE = 1.asUInt(3.W)
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val BTYPE = 2.asUInt(3.W)
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val UTYPE = 3.asUInt(3.W)
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val JTYPE = 4.asUInt(3.W)
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val SHAMT = 5.asUInt(3.W)
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val DC = 0.asUInt(3.W)
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}
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object ALUOps {
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val ADD = 0.U(4.W)
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val SUB = 1.U(4.W)
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val AND = 2.U(4.W)
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val OR = 3.U(4.W)
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val XOR = 4.U(4.W)
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val SLT = 5.U(4.W)
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val SLL = 6.U(4.W)
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val SLTU = 7.U(4.W)
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val SRL = 8.U(4.W)
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val SRA = 9.U(4.W)
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val COPY_A = 10.U(4.W)
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val COPY_B = 11.U(4.W)
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val DC = 15.U(4.W)
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}
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